1. Lecture #27 Page 1 ECE 4110– Sequential Logic Design Lecture #27 Agenda 1.Counters Announcements 1.HW #12 due.

2. Lecture #27 Page 2 Counters Counters - special name of any clocked sequential circuit whose state diagram is a circle - there are many types of counters, each suited for particular applications

3. Lecture #27 Page 3 Counters Binary Counter - state machine that produces a straight binary count - for n-flip-flops, 2 n counts can be produced - the Next State Logic "F" is a combinational SOP/POS circuit - the speed will be limited by the Setup/Hold and Combinational Delay of "F" - this gives the maximum number of counts for n-flip flops

4. Lecture #27 Page 4 Counters Toggle Flop - a D-Flip-Flop can product a "Divide-by-2" effect by feeding back Qn to D - this topology is also called a "Toggle Flop"

5. Lecture #27 Page 5 Counters Ripple Counter - Cascaded Toggle Flops can be used to form rippled counter - there is no Next State Logic - this is slower than a straight binary counter due to waiting for the "ripple" - this is good for low power, low speed applications

6. Lecture #27 Page 6 Counters Synchronous Counter with ENABLE - an enable can be included in a "Synchronous" binary counter using Toggle Flops - the enabled is implemented by AND'ing the Q output prior to the next toggle flop - this gives us the "ripple" effect, but also gives the ability to run synchronously - a little faster, but still less gates than a straight binary circuit

7. Lecture #27 Page 7 Counters Shift Register - a chain of D-Flip-Flops that pass data to one another - this is good for "pipelining" - also good for Serial-to-Parallel conversion - for n-flip-flops, the data is present at the final state after n clocks

8. Lecture #27 Page 8 Counters Ring Counter - feeding the output of a shift register back to the input creates a "ring counter" - also called a "One Hot" - The first flip-flop needs to reset to 1, while the others reset to 0 - for n flip-flops, there will be n counts

9. Lecture #27 Page 9 Counters Johnson Counter - feeding the inverted output of a shift register back to the input creates a "Johnson Counter" - this gives more states with the same reduced gate count - all flip-flops can reset to 0 - for n flip-flops, there will be 2n counts

10. Lecture #27 Page 10 Counters Linear Feedback Shift Register (LFSR) Counter - all of the counters based off of shift registers give far less states than the 2 n counts that are possible - a LFSR counter is based off of the theory of finite fields - created by French Mathematician Evariste Galois (1811-1832) - for each size of shift register, a feedback equation is given which is the sum modulo 2 of a certain set of output bits - this equation produces the input to the shift register - this type of counter can produce 2 n -1 counts, nearly the maximum possible

11. Lecture #27 Page 11 Counters Linear Feedback Shift Register (LFSR) Counter - the feedback equations are listed in Table 8.26 of the textbook - It is defined that bits always shift from X n-1 to X 0 (or Q 0 to Q n-1 ) as we defined the shift register previously - they each use XOR gates (sum modulo 2) of particular bits in the register chain ex) nFeedback Equation 2X2 = X1  X0 3X3 = X1  X0 4X4 = X1  X0 5X5 = X2  X0 6X6 = X1  X0 7X7 = X3  X0 8X8 = X4  X3  X2  X0 : : : :

12. Lecture #27 Page 12 Counters Linear Feedback Shift Register (LFSR) Counter ex) 4-flip-flop LFSR Counter Feedback Equation = X1  X0 (or Q2  Q3 as we defined it) #Q(0:3) Sin 0 1000 0 1 0100 0 2 0010 1 3 1001 1 4 1100 0 5 0110 1 6 1011 0 7 0101 1 8 1010 1 9 1101 1 10 1110 1 11 1111 0 12 0111 0 13 0011 0 14 0001 1- this is 2 n -1 unique counts repeat 1000