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Lecture 21 Overview Counters Sequential logic design

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Shift Register Often, however, the bits will not arrive in parallel but in serial - one bit at a time –Use a shift register –Input is applied to first flip-flop and shifted along one at each clock event –This example is a 4-bit shift register –It accepts serial input, stores the last 4 bits in the sequence and makes them available as parallel output Serial Input Parallel Output http://www.eelab.usyd.edu.au/digital_tutorial/part2/register03.html

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Digital counters: Ripple (Asynchronous) Counters Input Output Counters are sequential logic circuits that proceed through a well- defined sequence of states and then repeat. For a "divide-by-2" counter, simply connect the Q' output to the D input and feed an external clock signal in as the input: Input Output For a "divide-by-4" counter, connect 2 flipflops together in a chain: For a "divide-by-n" : connect 2 n flipflops together. Note that the FF outputs do not change at exactly the same time because of the propagation delay in each FF. These counters are known as ripple or asynchronous counters. +'ve edge-triggered D flipflop

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Synchronous Counters Connect all flip-flops to the same clock All flipflops change state at the same time (synchronous) A counter is a device which sequences through a fixed set of patterns in this case, 1000, 0100, 0010, 0001 (if one of these patterns is the initial state, defined by set/reset) Counts to n (n=number of flipflops) before repeating (ring counter) Mobius (or Johnson) Counter in this case, get 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000 counts to 2*n before repeating http://www.eelab.usyd.edu.au/digital_tutorial/part2/register07.html

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Binary Counter We normally want to count in a more useful fashion: e.g. binary This requires more combinational logic between the flipflops Need a rule for binary counting "The least significant bit always changes" "A bit changes state if all less significant bits are HIGH" Can implement this with an XOR gate Note Xxor1=X' DecimalBinaryHex 000000 100011 200102 300113 401004 501015 601106 701117 810008 910019 101010A 111011B 121100C 131101D 141110E 151111F A D ABCD So A + =Axor1, B + =BxorA, C + =CxorAB, D + =DxorABC

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Binary Down Counter How do you modify this circuit to count down? The rule is "The least significant bit always changes" "A bit changes state if all less significant bits are LOW" Note A XOR 1=A' A XNOR 0=A' DecimalBinaryHex 000000 100011 200102 300113 401004 501015 601106 701117 810008 910019 101010A 111011B 121100C 131101D 141110E 151111F A D So A + =Axor1, B + =BxnorA, C + =CxnorAB, D + =DxnorABC ABCD

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Pre-packaged Binary Counters Counters can be bought pre-packaged: e.g. a synchronous four-bit binary up/down-counter (e.g. DM74LS169A) Standard component with many applications Typical features: Positive edge-triggered FFs with synchronous LOAD and CLEAR inputs LOAD input allows parallel load of data from D, C, B, A CLEAR input resets outputs to 0000 EN input: must be asserted to enable counting RCO: ripple-carry output used for cascading counters High when counter is in its highest state 1111 Implemented using an AND gate: RCO= QA·QB·QC·QD EN D C B A LOAD CLK CLR RCO QD QC QB QA

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Binary Counters For an 8-bit synchronous binary up counter, cascade two 4-bit devices together Connect RCO from the first to EN of the second

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Offset Counters Two types; for a "starting offset counter" use the synchronous LOAD input. The counter counts like this: 0110,0111,1000,1001,1010,1011,1100,1101,1111,0110,... For an "ending offset counter" use a pattern recognizer for the ending value The counter counts like this: 0000,0001,0010,..., 1100,1101,0000,.... Load value 0110

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Sequential Logic Summary Fundamental building blocks of circuits with memory –latch and flipflop –R-S latch, R-S master-slave flipflop, D master-slave flipflop, edge-triggered D flipflop Timing Methodologies –use of clocks Basic registers –Storage register –Shift registers –pattern detectors –counters

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Sequential Logic Design Models for representing sequential circuits –Finite-state machines –Representation of memory (states) –Changes in state (transitions) Design procedure –State diagrams –State transition table –Next state functions

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Sequential Circuit Models: Abstraction of Circuit Elements Break the sequential circuit down into all its different elements External Inputs to combinational logic External Outputs from combinational logic Combinational logic Storage elements State Inputs to combinational logic State Outputs from combinational logic Combinational Logic Storage Elements External Outputs State OutputsState Inputs External Inputs

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Abstraction of Circuit Elements We often don’t have all of these Special case: No External Inputs E.g. Traffic light with no pedestrian control button Combinational Logic Storage Elements External Outputs State OutputsState Inputs

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Abstraction of State Elements Special case: No external outputs Output values correspond to state E.g.: Counters with LD, ENABLE, and CLR inputs Combinational Logic Storage Elements Outputs State Outputs State Inputs Inputs

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Abstraction of State Elements Special case: No explicit inputs or outputs E.g.: Counters without LD, ENABLE, and CLR inputs Combinational Logic Storage Elements Outputs State Outputs State Inputs

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Two Forms of Sequential Logic Asynchronous sequential logic – state changes occur whenever state inputs change (elements may be simple wires or delay elements) Hard to design due to race conditions, metastability. Rarely used. ignore it from now on. Synchronous sequential logic – state changes occur in step across all storage elements (using a periodic waveform - the clock) Clock Asynchronous Synchronous

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In = 0 In = 1 In = 0In = 1 100 010 110 111 001 Finite State Machine Representations A finite state machine model consists of: State Nodes (Circles): determined by possible values in sequential storage elements Transitions (Arrows): indicate a change of state; may or may not be associated with an input Clock: controls when state can change by controlling storage elements. Not explicitly shown. Sequential Logic Sequences through a series of states Based on a sequence of values of input signals Clock period defines elements of sequence

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Can Any Sequential System be Represented with a State Diagram? What about a Shift Register? Input value shown on transition arcs Output values shown within state node 100 110 111 011 101010 000 001 DQDQDQ IN OUT1OUT2OUT3 CLK

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Can Any Sequential System be Represented with a State Diagram? What about a Shift Register? Input value shown on transition arcs Output values shown within state node 100 110 111 011 101010 000 001 0 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 DQDQDQ IN OUT1OUT2OUT3 CLK

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010 100 110 011 001 000 101 111 3-bit up-counter Counters are Simple Finite State Machines Counters Simply cycle through a well-defined state sequence. Many types of counters: binary, BCD, Gray-code 3-bit up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000,... 3-bit down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111,... No inputs once started, no explicit outputs

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How Do We Turn a State Diagram into Logic? For a 3-bit counter: Need three flip-flops to hold state Need combinational logic to compute next state Clock signal controls when flip-flop memory can change Wait long enough for combinational logic to compute new value before providing the next clock event State Storage Logic

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FSM Design Procedure Start with counters Simple because the output is just the state Simple because there is no choice of next state based on inputs State diagram to state transition table Tabular form of state diagram Similar to a truth-table State encoding: how do you represent the state in binary? Decide on representation of states (e.g. traffic light green = what in binary?) For counters it is simple: just its value Implementation Flip-flop for each state bit Combinational logic based on state encoding

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current state next state 00000011 10010102 20100113 30111004 41001015 51011106 61101117 71110000 FSM Design Procedure: State Diagram to Encoded State Transition Table Transition table is just a tabular form of the state diagram Shows all of the possible transitions Like a truth-table (specify output for all input combinations) Encoding of states: easy for counters – just use output value 010 100 110 011 001 000 101 111 3-bit up-counter 0 123 4 567

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010 100 110 011 001 000 101 111 3-bit up-counter current state next state 00000011 10010102 20100113 30111004 41001015 51011106 61101117 71110000 FSM Design Procedure: State Diagram to Encoded State Transition Table Tabular form of state diagram Shows all of the possible transistions Like a truth-table (specify output for all input combinations) Encoding of states: easy for counters – just use output value

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C3C2C1N3N2N1 000001 001010 010011 011100 100101 101110 110111 111000 N1:= C1' N2:= C1C2' + C1'C2 := C1 xor C2 N3:= C1C2C3' + C1'C3 + C2'C3 := C1C2C3' + (C1' + C2')C3 := C1C2C3' + (C1C2)'C3 := (C1C2) xor C3 notation to show function representing input to D-FF Implementation Each state bit requires one D flip-flop Combinational logic is needed to implement transition table 01100110 10011001 C1 C2 C3 N2 1010 C1 C2 C3 N1 current next Karnaugh maps for each output: C2 0 000100011 11011101 C1 C3 N3 00 01 11 10 0 1 C3C2 C1

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C3C2C1N3N2N1 000001 001010 010011 011100 100101 101110 110111 111000 N1:= C1' N2:= C1C2' + C1'C2 := C1 xor C2 N3:= C1C2C3' + C1'C3 + C2'C3 := C1C2C3' + (C1' + C2')C3 := (C1C2) xor C3 Implementation currentnext Each state bit requires one D flip-flop Combinational logic is needed to implement transition table

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InC1C2C3N1N2N3 0000000 0001000 0010001 0011001 0100010 0101010 0110011 0111011 1000100 1001100 1010101 1011101 1100110 1101110 1110111 1111111 N1:= In N2:= C1 N3:= C2 Another Example Shift Register In the counter, current state (only) determines next state For a shift register Input + current state determines next state Need an extra column in the transition table 100 110 111 011 101010 000 001 0 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 DQDQDQ IN OUT1OUT2OUT3 CLK N1 N2N3C1C2C3 3-bit shift register. Serial input, parallel output.

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