6 Other octal registers 74x377 74x273 asynchronous clear Non-three state output74x377clock enableno tristate-buffer
7 Octal latch 74x373 Register vs. latch, what’s the difference? Output enableLatch-enable input “C” or “G”Register vs. latch, what’s the difference?Register: edge-triggered behaviorLatch: output follows input when G is asserted
8 Counters Any sequential circuit whose state diagram is a single cycle. RESET
13 74x163 internal logic diagram XOR gates embody the “T” functionMux-like structure for loading
14 Counter operation Free-running 16 Count if ENP and ENT both asserted. Load if LD is asserted (overrides counting).Clear if CLR is asserted (overrides loading and counting).All operations take place on rising CLK edge.RCO is asserted if ENT is asserted and Count = 15.