# 1 Lecture 15 Registers Counters Finite State Machine (FSM) design.

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1 Lecture 15 Registers Counters Finite State Machine (FSM) design

2 Registers Group of storage elements read/written as a unit  Store related values (e.g. a binary word) Collection of flip-flops with common control  Share clock, reset, set lines Example:  Storage registers  Shift registers  Counters

3 Storage registers Basic storage registers use flip-flops Example: 4 bit storage register RSRS DQDQDQ OUT1OUT2OUT3OUT4 CLK IN1IN2IN3IN4 RSRS DQ "0"

4 Shift registers Hold successively sampled input values  Delays values in time  Example: 4-bit shift register Stores 4 input values in sequence DQDQDQDQ IN OUT1OUT2OUT3OUT4 CLK

5 Shift register applications Parallel-to-serial conversion for signal transmission Pattern recognition (circuit recognizes 1001) parallel inputs parallel outputs serial transmission CLK DQDQDQDQ IN CLK OUT

6 Counters: Ring counter Ring counter: Sequence is 1000, 0100, 0010, 0001  Assuming one of these patterns is the starting state DQDQDQDQ IN OUT1OUT2OUT3OUT4 CLK

7 Counters: Johnson counter Johnson counter: Sequence is 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000 DQDQDQDQ IN OUT1OUT2OUT3OUT4 CLK

8 Counters: Binary counter Has logic between flip-flops Flip low-order bit each clock cycle Flip next bit in cycle when low- order bit is 1 Flip next bit when both lower order bits are 1 Flip next bit when all lower order bits are 1

9 Storing "states" for FSMs Combinational logic and storage elements  Localized feedback loops  Choice of storage elements alters the logic Combinational Logic Storage Elements Outputs State OutputsState Inputs Inputs

10 Finite-state machines (FSMs) States: Possible storage-element values Transitions: Changes in state  Clock synchronizes the state changes Sequential logic  Sequences through a series of states  Based on inputs and present state

11 FSM design example: Counters 1. Draw a state diagram 2. Draw a state-transition table 3. Encode the next-state functions  Minimize the logic using k-maps 4. Implement the design

12 1. Draw a state diagram 010 100 110 011 001 000 101 111 3-bit up-counter

13 2. Draw a state-transition table Like a truth-table  State encoding is easy for counters  Use count value current statenext state 00000011 10010102 20100113 30111004 41001015 51011106 61101117 71110000

14 3. Encode next state functions Assume D flip-flops as state elements N1:= C1' N2:= C1C2' + C1'C2 := C1 xor C2 N3:= C1C2C3' + C1'C3 + C2'C3 := C1C2C3' + (C1' + C2')C3 := (C1C2) xor C3 C3C2C1N3N2N1 000001 001010 010011 011100 100101 101110 110111 111000 0011010100110101 C2 C3 C1 N3 1111000011110000 C2 C3 C1 N1 0110100101101001 C2 C3 C1 N2

15 4. Implement the design 3 flip-flops hold state  Counter is synchronously clocked Minimized logic computes next state

16 What if we use T flip-flops? T flip-flops TQ C2C1C0N2N1N0 T2 T1 T0 000001 001010 010011 011100 100101 101110 110111 111000 0001000100010001 0101010101010101 1111111111111111 C1 C2 C0 T2 0 0 0 1 1 0 C1 C2 C0 T1 0 0 1 1 C1 C2 C0 T0 1 1 T0:= T1:= T2:= C0 C1 C0 1 Ti = 1 iff Ni ≠ Ci

17 4. Implement the design TQTQTQ C0C1C2 CLK 1

18 Example: 5-state counter Counter repeats 5 states in sequence  Sequence is 000, 010, 011, 101, 110, 000 000 010 011 101 110 Step 1: State diagramStep 2: State transition table Assume D flip-flops CBAC+B+A+ 000010 001X X X 010011 011101 100X X X 101110 110000 111X X X Present State Next State

19 3. Encode next state functions C B A 000XX1X1000XX1X1 C+ C B A 110XX0X1110XX0X1 B+ C B A 010XX1X0010XX1X0 A+ A+ = BC'C+ = AB+ = B' + A'C'

20 4. Implement the design Recall that a D flip flop also produces Q’ so A’, B’, and C’ would all be available without any extra inverters

21 Is our design robust? What if the counter starts in a 111 state? 001 100 111 Does our counter get stuck in invalid states??? 000 010 011 101 110

22 5-state counter Back-annotate our design to check it 000 010 011 101 110 Draw state diagramFill in state transition table CBAC+B+A+ 000010 001110 010011 011101 100010 101110 110000 111100 Present State Next State 001 100 111 The proper methodology is to design your counter to be self-starting A+ = BC' C+ = A B+ = B' + A'C'

23 Self-starting counters Invalid states should always transition to valid states  Assures startup  Assures bit-error tolerance Design your counters to be self-starting  Draw all states in the state diagram  Fill in the entire state-transition table  May limit your ability to exploit don't cares Choose startup transitions that minimize the logic

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