 # CHAPTER 3 Counters.  One of the common requirement in digital circuits/system is counting, both direction (forward and backward)  Digital clocks and.

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CHAPTER 3 Counters

 One of the common requirement in digital circuits/system is counting, both direction (forward and backward)  Digital clocks and watches are everywhere, timers are found in a range of appliances from microwave ovens to VCRs, and counters for other reasons are found in everything from automobiles to test equipment.  Although we will see many variations on the basic counter, they are all fundamentally very similar. The demonstration below shows the most basic kind of binary counting circuit. INTRODUCTION

 Counters can be implemented quite easily using register-type circuits such as the flip-flop, and a wide variety of classifications exist:  Asynchronous (ripple) counter – changing state bits are used as clocks to subsequent state flip-flops  Synchronous counter – all state bits change under control of a single clock  Decade counter – counts through ten states per stage  Up/down counter – counts both up and down, under command of a control input  Ring counter – formed by a shift register with feedback connection in a ring  Johnson counter – a twisted ring counter  Cascaded counter  Each is useful for different applications INTRODUCTION cont.

 A counter – a group of flip-flops connected together to perform counting operations.  The number of flip-flops used and the way in which they are connected determine the number of states (modulus).  Two broad categories according to the way they are clocked:  Asynchronous counter  Synchronous counter

ASYNCHRONOUS COUNTER A 2-bit asynchronous binary counter.  Don’t have fixed time relationship with each other.  Triggering don’t occur at the same time.  Don’t have a common clock pulse

The Timing diagram Notice that :  Main clock pulse only applied to FF0.  Clock for next FF, taken from previous complemented output ( Q ).  All inputs (J, K) are high (Vcc).

The Timing diagram

The Binary State Sequence CLOCK PULSEQ1Q1 Q0Q0 Initially00 101 210 311 4 (recycles)00 0 1 1 0 1 1 0 0 0 0

Three-bit asynchronous binary counter and its timing diagram for one cycle.

The Binary State Sequence for a 3-bit Binary Counter CLOCK PULSEQ2Q2 Q1Q1 Q0Q0 Initially000 1001 2010 3011 4100 5101 6110 7111 8 (recycles)000

Propagation delays in a 3-bit asynchronous (ripple- clocked) binary counter.

Four-bit asynchronous binary counter and its timing diagram.

ASYNCHRONOUS DECADE COUNTER  The modulus of a counter is the number of unique states that the counter will sequence through.  The maximum possible number of states (max modulus) is 2 n. Where n is the number of flip-flops.  Counter can also be designed to have a number of states in their sequence that is less than the maximum of 2 n. The resulting sequence is called truncated sequence.  Counter with ten states are called decade counter.  To obtain a truncated sequence it is necessary to force the counter to recycle before going through all of its possible states.

An asynchronously clocked decade counter Read example 9-2 page 465!! Modulus 12

The 74LS93A 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs are internally connected HIGH.)

SYNCHRONOUS COUNTER OPERATION A 2-bit synchronous binary counter.

Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assumed to be equal).

The Binary State Sequence CLOCK PULSEQ1Q1 Q0Q0 Initially00 101 210 311 4 (recycles)00 0 0 0 1 1 0 1 1 0 0

A 3-bit synchronous binary counter.

The Binary State Sequence for a 3-bit Binary Counter CLOCK PULSEQ2Q2 Q1Q1 Q0Q0 Initially000 1001 2010 3011 4100 5101 6110 7111 8 (recycles)000

A 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indicated by the shaded areas.

A 4-Bit Synchronous BCD Decade Counter.

The Binary State Sequence for BCD Decade Counter CLOCK PULSEQ3Q3 Q2Q2 Q1Q1 Q0Q0 Initially0000 10001 20010 30011 40100 50101 60110 70111 81000 91001 10 (recycles)0000

General clocked sequential circuit : DESIGN OF SYNCHRONOUS COUNTERS

Steps used in the design of sequential circuit: 1. Specify the counter sequence and draw a state diagram 2.Derive a next-state table from the state diagram 3.Develop a transition table showing the flip-flop inputs required for each transition. The transition table is always the same for a given type of flip-flop 4.Transfer the J and K states from the transition table to Karnaugh maps. There is a Karnaugh map for each input of each flip-flop. 5.Group the Karnaugh map cells to generate and derive the logic expression for each flip-flop input. 6.Implement the expressions with combinational logic, and combine with the flip-flops to create the counter.

State diagram for a 3-bit Gray code counter. 0 1 3 2 6 7 5 4 0 1.……..

Next-state table for a 3-bit Gray code counter. Present State Next State Q2Q2 Q1Q1 Q0Q0 Q2Q2 Q1Q1 Q0Q0 000001 001011 011010 010110 110111 111101 101100 100000

Transition Table for a J-K flip-flop Output TransitionsFlip-flop Inputs QNQN Q N+1 JK 0  00X 0  11X 1  0X1 1  1X0 Q N : present state Q N+1: next state X: Don’t care

Karnaugh maps for present-state J and K inputs.

Three-bit Gray code counter.

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