1. RF Modeling of Sub-100 nm CMOS S.Yoshizaki 1, M.Nakagawa 1, W.Y.Chong 1, Y.Nara 2, M.Yasuhira 2*, F.Ohtsuka 2, T.Arikado 2**, K.Nakamura 2, K.Kakushima 1, K.Tsutsui 1 H.Aoki 1, H.Iwai 1 1 Tokyo Institute of Technology 2 Semiconductor Leading Edge Technologies, Inc. (Selete), Japan * Current affiliation : Matsushita Electric Industrial Co., Ltd., Japan ** Current affiliation : Tokyo Electron Ltd., Japan

2. Fig.1 4-th Generation mobile  Center Research Laboratory, Hitachi Ltd.  Spread of the cellular phone and the wireless LAN.  The age of Digital information appliances  RF technologies serve the rapidly growing wireless communication markets. Background ~RF Technology~ Accurate RF Modeling become important to more than before. But …  ITRS2004update, 2004 Fig.2 Technology-development cost reduction (due to TCAD) In RF, some parasitic elements effect more severe.

3. Merit  Low cost compared with compound semiconductors  Consolidation with logic circuits Low operation voltage with scaling Scaling and Circuit technologies improve f T and f max Feature in RFCMOS Demerit SN ratio degradation Fig.3 Application Spectrum  ITRS2004, 2004

4. ① Degradation of dielectric constant with dielectric relaxation. ② RF characteristic deterioration with degrading mobility. ③ Increase interface state density → Increase Low-frequency noise and thus Phase noise. The concern about High-k MOSFET in RF

5. Motivation ► There are little reports about RF performance evaluation and modeling with High-k MOSFETs. ► Comparison HfSiON with SiON. RF Modeling of Sub-100 nm High-k MOSFET

6. Device ► EOT = 1.5nm (HfSiON & SiON) ► Gate length HfSiON (L g = 64nm), SiON (L g = 51nm) HfSiON (L g = 64nm), SiON (L g = 51nm) ► The number of finger = 12 （ W=5μm ） Fig.4 HfSiON MOSFET structure silicide HfSiON SiN Si silicide SiONSiN Si Fig.5 SiON MOSFET structure GGGGG SSSDD M1 STI VIA1 63.9nm 61.7nm 62.3nm 65.5nm 65.3nm Increase gate width with increasing number of fingers, the gate resistance become small. The number of finger N f : The number of finger Fig.6 Section of HfSiON MOSFET

7. DC Measurement and Simulation 【 HfSiON 】 Fig.7 Measured and simulated Ids-Vds 【 HfSiON 】 Vgs=0, 0.6, 0.9, 1.2, 1.5V MeasuredSimulated Fig.8 Measured Ids-Vds 【 SiON 】

8. To de-embed parasitic elements including wires and pads is important that could obtain the real device parameters. Rg Lg Cg Rgp CgdRgdp LdRd Cd Rdp Rs Ls DUT Drain SHORT De-embedding BSIM4 OPEN Gate Drain Gate Drain

9. Measured and Simulated f T, f max 【 HfSiON 】 f T,HfSiON = 189.9[GHz] f max,HfSiON = 59.9[GHz] Fig.9 H21 and GAmax vs. Frequency 【 HfSiON 】 Fig.10 Equivalent circuit model RgRg C GD C GS LDLD RDRD BSIM4 Measured GAmax Simulated GAmax Measured H21 Simulated H21 V g =1.2V, V d =1.5V

10. Measured S-parameter and Predicted f T, f max 【 SiON 】 f T,SiON = 236[GHz] f max,SiON = 74[GHz] Fig.11 H21 and GAmax vs. Frequency 【 SiON 】 Measured GAmax Extrapolated GAmax Measured H21 Extrapolated H21 V g =1.2V, V d =1.5V

11. RF Characterization ~ f T & g m Comparison HfSiON with SiON~ g m peak Cross SiON and HfSiON characteristics Fig.12 f T and g m vs. Id

12. Position of this device SiON HfSiON Gate Length [um] Fig.13 f T and f max  IEDM, VLSI 1995 ～ 2004

13.  We measured and simulated High-k MOSFET RF characteristics.  Measured from 500MHz to 40GHz, there is no dielectric relaxation.  Simulated f T and f max in HfSiON, we obtained good f T (189.9GHz) relatively.  SiON is expected much more high performance than HfSiON. I guess this is because of mobility degradation. Summary This work was partially supported by Special Coordination Funds for Promoting Science and Technology by Ministry of Education, Culture, Sports, Science and Technology, Japan. Acknowledgement

14. Id=1mA / Vd=0.1V Appendix A ~Flicker noise~ Fig.14 Flicker noise

15. 8 inch wafer, 40 GHz Appendix B ~ RF CMOS Evaluation Equipment ~