1. CS294-6 Reconfigurable Computing Day4 September 3, 1998 VLSI Scaling

2. Why Care? In this game, we must be able to predict the future Rapid technology advance Reason about changes and trends re-evaluate prior solutions given technology at time X.

3. Scaling Premise: features scale “uniformly” –everything gets better in a predictable manner Parameters: –  (lambda) -- Mead and Conway (class) –S -- Bohr –1/  -- Dennard

4. Feature Size

5. Scaling Channel Length (L) Channel Width (W) Oxide Thickness (T ox ) Doping (N a ) Voltage (V)

6. Scaling Channel Length (L) Channel Width (W) Oxide Thickness (T ox ) Doping (N a ) 1/ Voltage (V)

7. Effects? Area Capacitance Resistance Threshold (V th ) Current (I d ) Gate Delay (  gd ) Wire Delay (  wire ) Power

8. Area   L * W    m  m 50% area 2x capacity same area

9. Area Perspective

10. Capacitance Capacitance per unit area –C ox =  SiO 2 /T ox –T ox  T ox /  –C ox  C ox

11. Capacitance Gate Capacitance –C gate = A*C ox –   –C ox  C ox –C gate  C gate / 

12. Threshold Voltage

13. V TH  V TH 

14. Current Saturation Current –I d =(  C OX /2)(W/L)(V gs -V TH ) 2 –V gs= V  V  –V TH  V TH  –W  W  –C ox  C ox –I d  I d 

15. Gate Delay  gd =Q/I=(CV)/I V  V  I d  I d  C  C /   gd  gd / 

16. Resistance R=  L/(W*t) W  W  R  R

17. Wire Delay  wire =R L C R  R C  C /   wire  wire …assuming (logical) wire lengths remain constant...

18. Power Dissipation (Static) Resistive Power –P=V*I –V  V  –I d  I d  –P  P  

19. Power Dissipation (Dynamic) Capacitive (Dis)charging –P=(1/2)CV 2 f –V  V  –C  C /  –P  P   Increase Frequency? –f  f ? –P  P  

20. Effects? Area 1/   Capacitance 1/  Resistance  Threshold (V th ) 1/  Current (I d ) 1/  Gate Delay (  gd ) 1/  Wire Delay (  wire ) 1 Power 1/    1/  

21. Delays? If delays in gates/switching? If delays in interconnect? Logical interconnect lengths?

22. Delays? If delays in gates/switching? –Delay reduce with 1/ 

23. Delays Logical capacities growing Wirelengths? –No locallity  –Rent’s Rule L  n (p-0.5) [p>0.5]

24. Capacity Rent: IO=C*N p p>0.5 A  C*N 2p Logical Area     A  C*N 2 2p   N 2p  N 2 2p  N 2   p) N Sanity Check –p=1 –N 2  N –p~0.5 –N 2   N

25. Compute Density   >compute density scaling>     gates dominate, p<0.5    moderate p, good fraction of gate delay    large p (wires dominate area and delay)

26. Power Density P  P   (static, or increase frequency) P  P   (dynamic, same freq.)   P/A  P/A … or … P/  A

27. Scaling Summary Uniform scaling reasonably accurate for past couple of decades Area increase   –Real capacity maybe a little less? Gate delay decreases (1/  ) Wire delay not decrease, maybe increase Overall delay decrease less than (1/  )