1. San Jose January 23-24, 2001 Taipei February 14-15, 2001 DDR Penetrates Mobile Computing Bill Gervasi Technology Analyst Chairman, JEDEC Memory Parametrics Committee

2. Agenda Why DDR for Mobile? Standard versus cached DRAMs DDR Configurations Introducing the DDR MicroDIMM Mobile System Design Guidelines

3. Reasons for DDR in Mobile Performance Power Form factors

4. SDRAM Evolution 1000MB/s 2700MB/s Mainstream Memories SDR DDR333 Simple, incremental steps DDR II 4800MB/s 2100MB/s DDR266

5. Power: DDR vs SDR PC-100 1X DDR-266 3.2X PC-133 0.8X DDR-333 2.6X est.

6. DDR Power Management Relative Power CPU Clock Latency** Active on100%0 x 5 = 0 Inactive on 3 x 5 = 15 Active off 1 x 5 = 5 Inactive off0.2%4 x 5 = 20 Sleep 0.4%200 x 5=1000 Power State* 12% 4% * Not industry standard terms – simplified for brevity ** Assuming memory clock frequency = 1/5 CPU frequency Open Page Closed Page

7. Implications: Mobile Power Encourages closed page policy –Precharge banks as soon as data read –Takes latency hit to reactivate

8. Closed Page Power Profile NOPACTRRPRENOP ACTWWPRENOP Command Activity Power Profile Command Activity Lower Power Higher Power

9. Cached DRAM Power Profile NOPACTR-PRERRNOP ACTWWPRENOP Lower Power Higher Power Command Activity Power Profile Command Activity Depending on cached DRAM architecture

10. Standard vs Cached Cached DRAM architectures save power –Improved closed page performance –Latency reduction on page hits –Lower power profile (See my other presentation at Platform 2001… “An Analysis of Virtual Channel and Enhanced Memories Technologies”)

11. DDR Configurations TSOP-II SO-DIMM DIMM TQFP NEW! MicroDIMM NEW! FBGA

12. Next: Small Packages FBGA (fine pitch BGA) Lower inductance Lower capacitance Smaller footprint Tighter layouts enabled Details: Package size = 104 mm 2 = 54% smaller Inductance: 1.7nH lower Inductance variation, pin to pin: 3X less Capacitance: 0.5pF lower Performance gain: 300ps of data valid time

13. DDR Chip Configurations TQFP devices for point to point –x32 … 64Mb, 128Mb coming –100 pins, 16 x 22 mm footprint TSOP devices –x4, x8, x16 … 64Mb, 128Mb, 256Mb –66 pins, 12 x 22 mm footprint FBGA selection in process –x4, x8, x16 … 128Mb, 256Mb, 512Mb/1Gb coming –60 ball, 6.4 x 11 mm minimum footprint

14. DDR Module Configurations DDR SO-DIMM – done! –Sockets, modules in production DDR MicroDIMM – in process –Task group active System application combinations –One module only –Soldered down + module –Two modules

15. Next: DDR MicroDIMM Half the size of the DDR SO-DIMM Half the capacity if using TSOP – or – Same capacity if using FBGA Target markets: –PDAs –Internet appliances –Subnotebook computers

16. SO- and Micro- DIMMs DDR SO-DIMM TSOP: 67.6 x 31.75 mm = 2146 mm 2 4 or 8 devices 200 pins on 0.6 mm pin pitch (supports ECC) --------------------- FBGA: Under consideration if needed DDR MicroDIMM TSOP: 45.5 x 30 mm = 1365 mm 2 4 devices 172 pins on 0.5 mm pin pitch (no ECC) --------------------- FBGA: 45.5 x 25 mm = 1137 mm 2 4 or 8 devices

17. Module Status DDR SO-DIMM –DDR266 validated –DDR333 under analysis –Looking okay to 333 MHz with TSOP DDR MicroDIMM –TSOP easy, DDR266/333 speeds –FBGA package needed to fit 8 chips –Possible schedule Sample April 2001 Approved spec June 2001

18. Module Densities SO-DIMMMicroDIMM Raw Card 64 (Mb) 128 (Mb) 256 (Mb) Raw Card 64 (Mb) 128 (Mb) 256 (Mb) A: 8 TSOPs (MB) 64128256 A: 4 TSOPs (MB) 3264128 B: 8 TSOPs (MB) 64128256 B: 4 FBGAs (MB) 3264128 C: 4-5 TSOPs (MB) 3264128 C: 8 FBGAs (MB) 64128256

19. Small System Configurations One data bus, one address bus Point to point, single socket –Series damped data, address, clock Two sockets –SSTL_2 terminated data –Series damped address, clock –Top/bottom or butterfly arrangement

20. Top/Bottom Mobile Modules Standard for many current full size notebooks Hard to get at one of the modules Thickest form factor CPU Socket Module CPU ModuleSOCKET Motherboard Note: There may be patents regarding use of these layouts

21. Butterfly Mobile Modules Perfect for thin/light notebooks & subnotes Single access door to both modules Also good for small form factor desktop PCs CPU Module Socket CPU ModuleSOCKET Motherboard -- or -- Note: There may be patents regarding use of these layouts

22. MicroDIMM Designs You know the DDR SO-DIMM, so… …let’s focus on the MicroDIMM design First, system configurations…

23. Clock Topology RAM CK 25  Conn

24. Data Topology, 1 Slot RAM DQ, DQS, DM 25  Conn 22  2 bank

25. Data Topology, 2 Slot RAM DQ, DQS, DM 25  Conn 22  Conn RAM 22  25  V TT 2 bank

26. A/C Topology, 1 Slot RAM A, BA, WE, RAS, CAS 10  Conn RAM Two Bank MicroDIMM shown

27. A/C Topology, 1 Slot 10  Conn RAM 11pF One Bank MicroDIMM shown A, BA, WE, RAS, CAS

28. A/C Topology, 2 Slot 10  Conn RAM 11pF Two Bank MicroDIMM shown One Bank MicroDIMM shown A, BA, WE, RAS, CAS RAM

29. CS & CKE Topology CS, CKE 10  Conn RAM One or Two Bank MicroDIMM shown 11pF

30. Increasing Focus on Systems JEDEC packaging committee charter extended to include module sockets –Land pattern for pin pads –Mechanical support tab locations –Orientation holes –Shadow area of socket body –Module height & centerline Working system configuration first time!

33. DDR MicroDIMM Clearances Standard socket, double sided memory module Reverse socket, double sided memory module Reverse socket, single sided memory module Standard socket, single sided memory module 4.43mm max 0.65mm min 3.78mm max 5.40mm max 3.78mm max discretes

34. Socket Spec Status Merging 144, 172 pin sockets into single parameterized MO-214 spec –Priming spring included Shoves module “to the left” –Redimensioned by left edge, not center –Edge bevel defined

35. Conclusions DDR solutions for mobile growing Cached DRAM would be even better Point to point and DDR SO-DIMM done DDR333 development in progress FBGA packaged DDR coming DDR MicroDIMM development on track

36. Memory of choice for the future

37. Thank You