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Memory Design Considerations That Affect Price and Performance Bill Gervasi Technology Analyst, Transmeta Chairman, JEDEC Memory Parametrics

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Presentation on theme: "Memory Design Considerations That Affect Price and Performance Bill Gervasi Technology Analyst, Transmeta Chairman, JEDEC Memory Parametrics"— Presentation transcript:

1 Memory Design Considerations That Affect Price and Performance Bill Gervasi Technology Analyst, Transmeta Chairman, JEDEC Memory Parametrics

2 Posed at the Last Conference Why will DDR-I at 400 MHz data rate be a “boutique” solution? Why will DDR-II at 400 MHz data rate be a “mainstream” solution?

3 Agenda  JEDEC/Industry Roadmap  Factors for Market Acceptance  Difficulties in Achieving 400 MHz  Factors Affecting Cost  Wild Cards – What Can Change?

4 RAM Evolution 2100MB/s 2700MB/s Mainstream Memories DDR266 DDR333 Simple, incremental steps DDR MB/s DDR MB/s DDR MB/s “DDR I” “DDR II”

5 Factors for Market Acceptance  Industry Focus  Number of Competing Suppliers  JEDEC standard  Laws of Physics

6 Industry Focus  The JEDEC roadmap represents the industry focus for mainstream products  DDR-I tops out at 333 MHz data rate  DDR-II starts at 400 MHz data rate  This DOES NOT mean that DDR-I at 400 MHz data rate will not ship in volume  It DOES mean that there will be price premiums for this speed bin

7 What do I mean by “Focus”?  There is serious work to hit 400 MHz  Vendor interoperable solutions  Mix and match module configurations  Signal integrity analysis  We are counting picoseconds  No JEDEC standard yet proposed for DDR-I at 400 MHz data rate

8 For Example… How we are getting more refined in timing analysis with DDR-II… The Charge Transfer Model for input timing measurement and derating

9 DDR-I Input Timing Model INPUT SetupHold CLOCK Timing derating by input signal slew rate: 1.0V/ns = base value 0.5V/ns = base value + 50ps 0.4V/ns = base value + 100ps This got us through DDR333… The Old Way

10 However… This simplified model was good enough for DDR333 data rates, but leaves picoseconds of available timing lying around needed for 400+!!! DDR266 Data Setup/Hold = 750 ps DDR333 Data Setup/Hold = 600 ps DDR400 Data Setup/Hold = 400 ps DDR533 Data Setup/Hold = 350 ps Can’t waste time!!!

11 “Focus” on Input Timing INPUT DDR-II Charge Transfer Timing Model  All inputs have a slew rate dependent aspect t EXT and an independent aspect t INT  Summing t EXT + t INT gives input transition time t T  Transition time t T has min and max values  Differential input transitions inherently different t INT t EXT tTtT The New Way

12 t EXT for Slow Slew Rate, Single Ended V REF V IHAC = V SAT V IHDC V ILDC V ILAC= V SAT t EXT A T = Charge to Transition t INT

13 t EXT for Fast Slew Rate, Single Ended V REF V IHAC = V SAT V IHDC V ILDC V ILAC = V SAT t EXT t SAT A SAT = Charge to Saturation A ADD = Charge after Saturation A T = A SAT + A ADD V SAT = Saturation Voltage t INT

14 t EXT for Slow Slew Rate, Differential V REF V IHAC = V SAT V IHDC V ILDC V ILAC = V SAT A T = Charge to Transition t EXT t INT

15 t EXT for Fast Slew Rate, Differential V REF V IHAC = V SAT V IHDC V ILDC V ILAC = V SAT A T = A SAT + A ADD t EXT t INT

16 “Focus” on Timing INPUT Setup CLOCK DDR-II Charge Transfer Timing Model Setup = t T max of input - t T min of reference t T max t T min

17 “Focus” on Timing INPUT Hold CLOCK DDR-II Charge Transfer Timing Model Hold = t T max of reference - t T min of input t T min t T max

18 How does this help…? The Charge Transfer Model gives a higher accuracy for setup and hold relationships It also provides a way to accurately describe derating for input slew rate These models are negotiated with all suppliers to define an industry standard

19 DDR-II Input Derating Tables Strobe (mV/ps avg) Data (mV/ps) Clock (mV/ps avg) Addr (mV/ps) HOLD SETUP HOLD    Strobe (mV/ps avg) Data (mV/ps) Clock (mV/ps avg) Addr (mV/ps)  + +       0 +  + +   + 

20 Derating Using Charge Transfer  Accuracy from derating both signals and references  Result is a two dimensional matrix relating inputs & their references  Identified inherent asymmetries in derating of setup & hold when mixing single ended with differential signals  Memory module mixes impact slew rates  The Charge Transfer model controls system cost by enabling more complex timing analysis

21 Charge Transfer on DDR-I?  This model would also help design high speed DDR-I systems  However, the work to retrofit this to DDR-I needs to be done to benefit from it

22 DDR-II Improvements DDR-II introduces technical improvements that reduce the cost of achieving high speeds  Prefetch 4  Differential data strobe  I/O Calibration  Lower I/O Voltage  On-Die Termination

23 Prefetch 4

24 Moving to the Next Level  Today’s SDRAM architectures assume an inexpensive DRAM core timing  DDR I (DDR200, DDR266, and DDR333) prefetches 2 data bits: increase performance without increasing timing costs  DDR II (DDR400, DDR533, DDR667) prefetches 4 bits internally, but keeps DDR double pumped I/O

25 Prefetch 2 Versus 4 CK READ Prefetch 2 Prefetch 4 Core access time Costs $$$ Essentially free data Column cycle time Costs $$$

26 Prefetch Impact on Cost By doubling the prefetch depth, cycle time for column reads & writes relaxed, improving DRAM yields DDR-I DDR-II Pre- fetch ns 6 ns 5 ns 6 ns 7.5 ns 10 ns DDR Family Data Rate Cycle Time Starts to get REAL EXPENSIVE! Comparable to DDR266 in cost

27 Why Not Prefetch = 8?  DIMM width = 64 bits  PCs use 64b, servers use 128b (2 DIMMs)  64 byte prefetch okay for PC, but…  128 byte prefetch for servers wastes bandwidth  DDR-II must service all applications well to insure maximum volume  minimum cost

28 Differential Data Strobe

29  Just as DDR added differential clock to SDR  DDR II adds differential data strobe to DDR I  Transition at the crosspoint of DQS and DQS

30 Differential Data Strobe DQS high time V REF DQS low time DQS DQS high time V REF DQS low time DQS Normal balanced signal Mismatched Rise & Fall signal Error!

31 Differential Data Strobe DQS high time V REF DQS low time DQS DQS high time V REF DQS low time DQS Normal balanced signal Mismatched Rise & Fall signal DQS Significantly reduced symmetry error

32 I/O Calibration

33  Balance pull-up and pull-down driver strength  Reduces timing errors from signal asymmetry  Insures signal rise and fall times are similar Reference Data Controller DRAM

34 1.8V I/O Voltage

35 1.8V Signaling 2.5V SSTL_ V 0.90V 1.43V 1.07V 1.25V 0V 0.90V 1.03V 0.77V 0.65V 1.15V 1.8V VSS VDDQ VREF VIHac VIHdc VILdc VILac VREF VSS VDDQ VIHac VIHdc VILdc VILac SSTL_2

36 I/O Voltage Impact on Timing  Assume 1mV/ps edge slew rate  DDR-I = 700 mV (V IL  V IH ) = 700 ps  DDR-II = 500 mV (V IL  V IH ) = 500 ps  Helps meet the need for speed  Signal integrity is a serious challenge at DDR-I and 400 MHz data rate

37 On-Die Termination

38 Reduces system cost while improving signal integrity Data Controller V TT = V DD Q  2 DRAM Data Controller DRAM VDDQ  2 DDR-I DDR-II

39 What Can Change?

40 Wild Cards  100% yield of 5 ns cycle time cores (magic?)  Industry gets excited about engineering DDR-I at 400 MHz  DDR-II slow transition from schedule or price  Feature creep  Die penalties  DRAM guys trying to make money for once

41 Conclusions  DDR-I at 400 will ship in volume but  …not likely to cross over $/bit  Industry focus is on transition to DDR-II for 400+ MHz data rates

42 Thank You


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