4 Key to System Evolution Never over-design!Implement just enough new features to achieve incremental improvementsUse low cost high volume infrastructureProcessesPackagesPrinted circuit boards
5 From SDR to DDR Prefetch 2 Prefetch 2 Differential Clocks Signaling & PowerWrite LatencyWhen considering migrating a design from SDR to DDR, the five primary factors to consider are signaling, clocks, data strobe, packages, and total pin count.Data Strobe
6 PrefetchToday’s SDRAM architectures assume an inexpensive DRAM core timingDDR I (DDR200, DDR266, and DDR333) prefetches 2 data bits: increase performance without increasing core timing costsDDR II (DDR400, DDR533, DDR667) prefetches 4 bits internally, but keeps DDR double pumped I/ODDR-I 400 is a prefetch-2 architecture
7 Prefetch Depth CK data READ Core access time Costs $$$ SDR: Prefetch 1Core access timeDDR-I: Prefetch 2DDR-II: Prefetch 4Costs $$$Column cycle timeEssentially freeCosts $$$
8 Prefetch Impact on Cost SDRAM FamilyPre- fetchData RateCycle TimeHigh Yield =Affordable110010 nsSDR11337.5 ns220010 nsDDR-I22667.5 nsStarts to get REAL EXPENSIVE!23336 ns24005 nsDDR-II440010 ns45337.5 nsComparable to DDR266 in cost
9 DDR Data TimingData valid on rising & falling edges… “Double Data Rate”Source Synchronous; Data Strobe “DQS” travels with dataDouble data rate signals are sampled at both edges of the clock. Since the clock loading is different from the data loading, it makes a poor choice for a strobe. Hence, a new data strobe signal (DQS) is introduced.DQS is driven by the controller during data write operations, and driven by the SDRAM during data read operations. The DQS signal is loaded exactly like the data lines, therefore exhibits identical electrical characteristics.DDR SDRAMs also provide an on-chip DLL that keeps the delivery of DQS and the data during read operations synchronized to the clock input to the DDR SDRAM. This allows two significant designer choices: operating massive systems like servers with an echo clock, or operating fully synchronous systems that must capture return data in a single clock period.Another enhancement from the user perspective is a guarantee by specification of the width of a data window to insure sufficient time to capture that data. This parameter, tDV, guarantees that jitter will not close the data valid eye.
10 From SDR to DDR Prefetch 2 Differential Clocks Differential Clocks Signaling & PowerWrite LatencyWhen considering migrating a design from SDR to DDR, the five primary factors to consider are signaling, clocks, data strobe, packages, and total pin count.Data Strobe
11 DDR Clocks Differential clocks on adjacent traces Timing is relative to crosspointHelps ensure 50% duty cycleDDR uses a differential clock in order to deliver a nearly perfect square wave to the DDR SDRAM internal circuits. Running clock and its complement on adjacent traces from controller to the DDR SDRAM enhances signal quality through common mode rejection.For simplicity in reading the diagrams, subsequent drawings will only show the CK signal, but it is understood that this refers to the crosspoint of the clock CK and its complement /CK.
12 Single Ended Clock VREF CK Clock high time Clock low time VREF CK Normal balanced signalVREFCKClock high timeClock low timeMismatched Rise & Fall signalError!
13 Significantly reduced symmetry error Differential ClockCKCKClock high timeClock low timeNormal balanced signalCKCKClock high timeClock low timeMismatched Rise & Fall signalSignificantly reduced symmetry error
14 From SDR to DDR Prefetch 2 Differential Clocks Signaling & Power Write LatencyWhen considering migrating a design from SDR to DDR, the five primary factors to consider are signaling, clocks, data strobe, packages, and total pin count.Data Strobe
15 DDR Signaling SSTL_2 low voltage swing inputs 2.5V I/O with 1.25V reference voltageLow voltage swing with terminationRail to rail if unterminatedSSTL_2 signals trigger high and low levels as a few millivolts off a central voltage reference. With simple resistor termination networks to a termination voltage, VTT, equal to the reference voltage, low voltage signaling appears on the transmission lines.If the termination resistors are eliminated, the SSTL_2 signals run rail to rail, with 2.5V swings. Voltage levels for high and low are still recognized and the system operates fine.
16 Keys to low power design: Power = CV2f%#Factors:Capacitance (C)Voltage (V)Frequency (f)Duty cycle (%)Power states (# circuits in use)Keys to low power design:Reduce C and VMatch f to demandMinimize duty cycleUtilize power states
18 From SDR to DDR Prefetch 2 Differential Clocks Signaling & Power Write LatencyWhen considering migrating a design from SDR to DDR, the five primary factors to consider are signaling, clocks, data strobe, packages, and total pin count.Data StrobeData Strobe
19 Emphasis on “Matched” DM/DQS loading identical to DQ CONTROLLERDDR SDRAMDQ/DQSVREFVREFDMVREFA key performance enhancement in DDR comes from thinking of a 64bit bus as eight semi-independent 8bit buses consisting of 8 data lines DQ, one data strobe DQS, and one data mask DM. Within each group of 10 pins, length, loading, and termination should be balanced as accurately as possible. This includes the DM, which though used only for data writes, should have a fake read channel that is never used to insure identical loading to the bidirectional DQ and DQS lines.In this way, controller input circuits will see minimal skew between signals, and can resynchronize all data groups to the internal timing of the controller.VREFDisableDM/DQS loading identical to DQRoute as independent 8bit buses
20 Copper from controller to SDRAMs Sync to Controller clock 64 = 8 x 864bit bus is 8 sync’ed 8bit busesAllows external “copper” flexibility8 buses resync upon entry to FIFOx16 DDR SDRAMx16 DDR SDRAMx16 DDR SDRAMx16 DDR SDRAMCopper from controller to SDRAMs8 DQ 1 DM 1 DQS8 DQ 1 DM 1 DQS8 DQ 1 DM 1 DQSInside Controller8bit Buffer8bit BufferSync to Controller clock64bit Memory Controller Internal FIFO
21 From SDR to DDR Prefetch 2 Differential Clocks Signaling & Power Write LatencyWrite LatencyWhen considering migrating a design from SDR to DDR, the five primary factors to consider are signaling, clocks, data strobe, packages, and total pin count.Data Strobe
22 Write Latency SDR had to keep inputs powered all the time Adding Write Latency to DDR allowed inputs to be powered off between commandsFlexible timing differences on data and address paths
24 DDR-I 400 Summary DDR-I is hard to design to 400 MHz data rate Lower yieldsNo JEDEC standardPrefetch-2, 2.5V signals, TSOP packages, write latency 1DDR-II makes it a lot easierJEDEC standards & focusPrefetch-4, 1.8V signals, differential strobeOn-die termination, BGA packages, write latency > 1Same plane referencingFew suppliers supporting DDR-I 400 market
25 DDR-I 400 ConclusionThe JEDEC roadmap represents the industry focus for mainstream productsDDR-I tops out at 333 MHz data rateDDR-II starts at 400 MHz data rateThis DOES NOT mean that DDR-I at 400 MHz data rate will not ship in volumeIt DOES mean that there will be price premiums for this speed bin
26 Market Outlook DDR-I DDR-II DDR333 is the mainstream product for 2003 DDR-I 400 will be the premium marketDDR-IIDDR-II designs under way nowDDR-II 400 & 533 will sample in 2003DDR-II ramp begins in 2004
27 Summary DDR has many improvements over SDR Prefetch, differential clock, low voltage, data strobe, write latencyDDR-I 400 likely to stay a profitable nicheDDR-II volume products for 400 & 533 ramp in 2004