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1 Introduction to DDR SDRAM Bill Gervasi Technology Analyst

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Presentation on theme: "1 Introduction to DDR SDRAM Bill Gervasi Technology Analyst"— Presentation transcript:

1 1 Introduction to DDR SDRAM Bill Gervasi Technology Analyst

2 2 Topics to Cover The SDRAM Roadmap Transitioning from SDR to DDR DDR-I 400 Overview Market overview

3 3 SDRAM Evolution Simple, incremental steps DDR I DDR II 1100MB/s PC133 DDR MB/s DDR MB/s DDR MB/s 1600MB/s DDR200 SDR DDR MB/s DDR400? 3200MB/s Mainstream Memories DDR MB/s

4 4 Key to System Evolution Never over-design! Implement just enough new features to achieve incremental improvements Use low cost high volume infrastructure –Processes –Packages –Printed circuit boards

5 5 From SDR to DDR Signaling & Power Differential Clocks Data Strobe Prefetch 2 Write Latency Prefetch 2

6 6 Prefetch Todays SDRAM architectures assume an inexpensive DRAM core timing DDR I (DDR200, DDR266, and DDR333) prefetches 2 data bits: increase performance without increasing core timing costs DDR II (DDR400, DDR533, DDR667) prefetches 4 bits internally, but keeps DDR double pumped I/O DDR-I 400 is a prefetch-2 architecture

7 7 Prefetch Depth CK READ Core access time Costs $$$ Essentially free data SDR: Prefetch 1 DDR-I: Prefetch 2 DDR-II: Prefetch 4 Costs $$$ Column cycle time

8 8 Prefetch Impact on Cost SDR DDR-II Pre- fetch ns 7.5 ns 10 ns 7.5 ns 10 ns 7.5 ns SDRAM Family Data Rate Cycle Time Comparable to DDR266 in cost DDR-I ns ns Starts to get REAL EXPENSIVE! High Yield = Affordable

9 9 DDR Data Timing Data valid on rising & falling edges… Double Data Rate Source Synchronous; Data Strobe DQS travels with data

10 10 From SDR to DDR Signaling & Power Differential Clocks Data Strobe Prefetch 2 Write Latency Differential Clocks

11 11 DDR Clocks Differential clocks on adjacent traces Timing is relative to crosspoint Helps ensure 50% duty cycle

12 12 Single Ended Clock Clock high time V REF Clock low time CK Clock high time V REF Clock low time CK Normal balanced signal Mismatched Rise & Fall signal Error!

13 13 Differential Clock Significantly reduced symmetry error Clock high time Clock low time CK Clock high time Clock low time CK Normal balanced signal Mismatched Rise & Fall signal CK

14 14 From SDR to DDR Signaling & Power Differential Clocks Data Strobe Prefetch 2 Write Latency Signaling & Power

15 15 DDR Signaling SSTL_2 low voltage swing inputs –2.5V I/O with 1.25V reference voltage –Low voltage swing with termination –Rail to rail if unterminated

16 16 Power = CV 2 f%# Factors: Capacitance (C) Voltage (V) Frequency (f) Duty cycle (%) Power states (# circuits in use) Keys to low power design: Reduce C and V Match f to demand Minimize duty cycle Utilize power states

17 17 Power: SDR DDR-I DDR-II 3.3V 1.8V 2.5V

18 18 From SDR to DDR Signaling & Power Differential Clocks Data Strobe Prefetch 2 Write Latency Data Strobe

19 19 Emphasis on Matched DM/DQS loading identical to DQ Route as independent 8bit buses DQ/DQS DM V REF Disable CONTROLLER DDR SDRAM

20 20 64 = 8 x 8 64bit bus is 8 synced 8bit buses Allows external copper flexibility 8 buses resync upon entry to FIFO 8 DQ 1 DM 1 DQS 8bit Buffer 8 DQ 1 DM 1 DQS x16 DDR SDRAM 64bit Memory Controller Internal FIFO Sync to Controller clock Copper from controller to SDRAMs Inside Controller x16 DDR SDRAM 8 DQ 1 DM 1 DQS

21 21 From SDR to DDR Signaling & Power Differential Clocks Data Strobe Prefetch 2 Write Latency

22 22 Write Latency SDR had to keep inputs powered all the time Adding Write Latency to DDR allowed inputs to be powered off between commands Flexible timing differences on data and address paths

23 23 DDR-I vs 400 DDR I DDR II DDR MB/s DDR MB/s DDR400? 3200MB/s

24 24 DDR-I 400 Summary DDR-I is hard to design to 400 MHz data rate –Lower yields No JEDEC standard Prefetch-2, 2.5V signals, TSOP packages, write latency 1 –DDR-II makes it a lot easier JEDEC standards & focus Prefetch-4, 1.8V signals, differential strobe On-die termination, BGA packages, write latency > 1 Same plane referencing Few suppliers supporting DDR-I 400 market

25 25 DDR-I 400 Conclusion The JEDEC roadmap represents the industry focus for mainstream products –DDR-I tops out at 333 MHz data rate –DDR-II starts at 400 MHz data rate This DOES NOT mean that DDR-I at 400 MHz data rate will not ship in volume It DOES mean that there will be price premiums for this speed bin

26 26 Market Outlook DDR-I –DDR333 is the mainstream product for 2003 –DDR-I 400 will be the premium market DDR-II –DDR-II designs under way now –DDR-II 400 & 533 will sample in 2003 –DDR-II ramp begins in 2004

27 27 Summary DDR has many improvements over SDR –Prefetch, differential clock, low voltage, data strobe, write latency DDR-I 400 likely to stay a profitable niche DDR-II volume products for 400 & 533 ramp in 2004

28 28 Thank You


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