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Posted CAS for DDR-II SDRAM Bill Gervasi Technology Analyst October, 2002 Posted CAS.

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Presentation on theme: "Posted CAS for DDR-II SDRAM Bill Gervasi Technology Analyst October, 2002 Posted CAS."— Presentation transcript:

1 Posted CAS for DDR-II SDRAM Bill Gervasi Technology Analyst October, 2002 Posted CAS

2 Traditional DDR-I SDRAM RAS and CAS (read/write) issued independently RAS and CAS (read/write) issued independently Controllers must insure the command bus is free Controllers must insure the command bus is free If collisions would occur, next command is delayed If collisions would occur, next command is delayed Command streams and arbitration are complex Command streams and arbitration are complex CK RASCAS Data tRCDCAS Latency

3 DDR-I Command Stream Shows string of commands to one DRAM extent Shows string of commands to one DRAM extent RAS 2 delay of 1 clock results in a delay of 2 clocks (to avoid landing on top of CAS 1 ) RAS 2 delay of 1 clock results in a delay of 2 clocks (to avoid landing on top of CAS 1 ) Data gap after D 1 data caused by command gap Data gap after D 1 data caused by command gap Assumed: Page closed policy, tRCD=3, CL=2, BL=4 CK RASCASRASCAS RAS Data D D D D D 0 D 0 D 0 D 0 Command Gap

4 DDR-II Posted CAS for Reads Delay the internal execution of the CAS command Delay the internal execution of the CAS command RAS/CAS commands can be issued back to back RAS/CAS commands can be issued back to back CK Data RASCAS tRCD CAS Latency Additive Latency Read Latency = AL + CL READ

5 DDR-II Posted CAS for Writes Delay from write command to data tied to CAS Latency Delay from write command to data tied to CAS Latency Maintains write-to-read & read-to-write timing relationship Maintains write-to-read & read-to-write timing relationship CK Data RASCAS tRCD CL - 1 Additive Latency Write Latency = RL - 1 WRITE

6 DDR-II Command Stream Shows string of commands to one DRAM extent Shows string of commands to one DRAM extent RAS 2 delay of 1 clock results in a delay of 1 clock (no collision to avoid, no additional delay) RAS 2 delay of 1 clock results in a delay of 1 clock (no collision to avoid, no additional delay) Data gap of 1 command clock between RAS 1 /CAS 1 and RAS 2 /CAS 2 occurs later in time Data gap of 1 command clock between RAS 1 /CAS 1 and RAS 2 /CAS 2 occurs later in time Assumed: Page closed policy, tRCD=3, AL=2, CL=2, BL=4 CK RASCASRASCASRAS CAS Data D 1 D 0 D 0 D 0 D 0

7 Open Versus Closed Page Closed page systems Auto Precharge –Requires RAS and t RCD to reopen same row Open page systems do not issue Precharge if there is a good chance the same page will be accessed again –Avoids need for RAS and t RCD RASCAS/APRASCAS/APRASCAS/AP RASCAS PRE t RCD

8 Posted CAS with Open Page Additive latency still included though not needed Additive latency still included though not needed In this case, Posted CAS reduces performance In this case, Posted CAS reduces performance CK Data RASCAS CAS Latency Additive Latency Read Latency CAS CAS Latency Additive Latency Read Latency Data would appear here without Posted CAS

9 Posted CAS Summary Closed Page Policy Closed Page Policy Allows RAS & CAS to be issued back to back Allows RAS & CAS to be issued back to back No impacts to latency (from RAS) No impacts to latency (from RAS) No command collisions No command collisions Longer write recovery Longer write recovery Open Page Policy Open Page Policy Not likely to be used due to increased latency (from CAS) Not likely to be used due to increased latency (from CAS) Disable Posted CAS via programming register Disable Posted CAS via programming register

10 DDR-II Read to Read, Posted CAS Internal bank to internal bank CK RASCASRASCAS Data D 1 D 0 D 0 D 0 D 0 D 1 D 1 RL RASCASRASCAS 0101 CK Data D 0 D 0 D 0 D 0 RL Device to device, same databus Device Handoff Gap

11 DDR-II Read to Write, Posted CAS RASCASRASCAS 0101 CK Minimum interleave, bus limited, applies to all situations Data D 0 D 0 D 0 D 0 RL D 1 D 1 D 1 WL

12 DDR-II Write to Read, Posted CAS Device to device, same databus RASCASRASCAS WL CLK Data D 0 D 0 D 0 D 0 D 1 D 1 Internal bank to internal bank RAS CASRAS CAS CK WL Data D 0 D 0 D 0 D 0 (CL tWTR) W/R Turnaround Gap

13 DDR-II Write to Write, Posted CAS Internal bank to internal bank or device to device with MBT* Device to device, same data bus with ODT* CK RASCASRASCAS Data D 1 D 0 D 0 D 0 D 0 D 1 D 1 WL RAS CAS 1 RAS 1 CAS 00 CK Data WL D 0 D 0 D 0 D 0 D 1 ODT Shift Gap * MBT = Motherboard Termination * ODT = On-Die Termination

14 Conclusions: Posted CAS reduces command bus collisions Posted CAS reduces command bus collisions Results in higher data throughput Results in higher data throughput Optimized with WL = RL - 1 for maximum data bus utilization Optimized with WL = RL - 1 for maximum data bus utilization Can be disabled for open page systems Can be disabled for open page systems Simple concept, easy control, great benefit Simple concept, easy control, great benefit


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