1. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 1 Finite State Machines (FSM) Sequential circuits  primitive sequential elements  combinational logic Models for representing sequential circuits  finite-state machines (Moore and Mealy) Basic sequential circuits revisited  shift registers  counters Design procedure  state diagrams  state transition table  next state functions Hardware description languages

2. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 2 Abstraction of state elements Divide circuit into combinational logic and state Localize the feedback loops and make it easy to break cycles Implementation of storage elements leads to various forms of sequential logic Combinational Logic Storage Elements Outputs State OutputsState Inputs Inputs

3. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 3 Forms of sequential logic Asynchronous sequential logic – state changes occur whenever state inputs change (elements may be simple wires or delay elements) Synchronous sequential logic – state changes occur in lock step across all storage elements (using clock) Clock

4. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 4 In = 0 In = 1 In = 0In = 1 100 010 110 111 001 Finite state machine representations States: determined by possible values in sequential storage elements Transitions: change of state Clock: controls when state can change by controlling storage elements Sequential logic  sequences through a series of states  based on sequence of values on input signals  clock period defines elements of sequence

5. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 5 Can any sequential system be represented with a state diagram? Shift register  input value shown on transition arcs  output values shown within state node 100 110 111 011 101010 000 001 1 1 1 1 0 0 0 0 1 1 1 0 0 1 0 0 DQDQDQ IN OUT1OUT2OUT3 CLK

6. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 6 010 100 110 011 001 000 101 111 3-bit up-counter Counters are simple finite state machines Counters  proceed through well-defined sequence of states in response to enable Many types of counters: binary, BCD, Gray-code  3-bit up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000,...  3-bit down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111,...

7. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 7 How do we turn a state diagram into logic? Counter  3 flip-flops to hold state  logic to compute next state  clock signal controls when flip-flop memory can change wait long enough for combinational logic to compute new value don't wait too long as that is low performance

8. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 8 FSM design procedure Start with counters  simple because output is just state  simple because no choice of next state based on input State diagram to state transition table  tabular form of state diagram  like a truth-table State encoding  decide on representation of states  for counters it is simple: just its value Implementation  flip-flop for each state bit  combinational logic based on encoding

9. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 9 J-K Flipflop How to eliminate the forbidden state? Idea: use output feedback to guarantee that R and S are never both one J, K both one yields toggle Characteristic Equation: Q+ = Q K + Q J S(t) 0 1 R(t) 0 1 0 1 Q(t) 0 1 0 1 0 1 0 1 Q(t+∆) 0 1 0 1 X HOLD RESET SET TOGGLE

10. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 10 C hoosing a Flipflop R-S Clocked Latch: used as storage element in narrow width clocked systems its use is not recommended! however, fundamental building block of other flipflop types J-K Flipflop: versatile building block can be used to implement D and T FFs usually requires least amount of logic to implement ƒ(In,Q,Q+) but has two inputs with increased wiring complexity because of 1's catching, never use master/slave J-K FFs edge-triggered varieties exist D Flipflop: minimizes wires, much preferred in VLSI technologies simplest design technique best choice for storage registers T Flipflops: don't really exist, constructed from J-K FFs usually best choice for implementing counters Preset and Clear inputs highly desirable!!

11. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 11 010 100 110 011 001 000 101 111 3-bit up-counter present state next state 00000011 10010102 20100113 30111004 41001015 51011106 61101117 71110000 FSM design procedure: state diagram to encoded state transition table Tabular form of state diagram Like a truth-table (specify output for all input combinations) Encoding of states: easy for counters – just use value

12. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 12 More complex counter example Complex counter  repeats 5 states in sequence  not a binary number representation Step 1: derive the state transition diagram  count sequence: 000, 010, 011, 101, 110 Step 2: derive the state transition table from the state transition diagram Present StateNext State CBAC+B+A+ 000010 001XXX 010011 011101 100XXX 101110 110000 111XXX note the don't care conditions that arise from the unused state codes 010 000110 101 011

13. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 13 010 000110 101 011 Self-starting counters (cont’d) 1 Present State Next State CBAC+B+ 1 A+ 000 00 00 0 00 0 0 1 11 1 11 11 111 00 0 0 0 000 11 11 11 CB 0001 11 10A 0 1 C+ = CB 0001 11 10A 0 1 A+ = CB 0001 11 10A 0 1 B+ = 000 0 0 0 0 0 11 11 1 1 1 XX X XX X X XX C CC B B B

14. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 14 Excitation Tables: What are the necessary inputs to cause a particular kind of change in state? D 0 1 0 1 T 0 1 1 0 Q + 0 1 0 1 Q 0 0 1 1 S 0 1 0 X R X 0 1 0 K X X 1 0 J 0 1 X X

15. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 15 Toggle Excitation Table Remapped Next State Functions Q0011Q0011 Q+ 0 1 0 1 T0110T0110 Present State Toggle Inputs C00001111C00001111 B00110011B00110011 A01010101A01010101 TC 0 X 0 1 X 0 1 X TB 1 X 0 1 X 1 X TA 0 X 1 0 X 1 0 X Using T Flipflops:

16. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 16 TC = A C + A C = A xor C TB = A + B + C TA = A B C + B C CB 0001 11 10A 0 1 TC CB 0001 11 10A 0 1 TA CB 0001 11 10 A 0 1 TB 00 0 0 00 0 1 1 1 1 1 1 1 1 X X X XX X XX X C C C B B B Using T Flipflops:

17. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 17 Resulting Logic: 5 Gates 13 Input Literals + Flipflop connections TC T CLK Q Q S R Count T CLK Q Q S R TB C \C BA \B \A TA T CLK Q Q S R \Reset 1 0 A C A \B C TC TB \A B \C \B C TA Using T Flipflops:

18. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 18 Excitation Table Remapped Next State Functions Q0011Q0011 Q+ 0 1 0 1 D0101D0101 Using D Flipflops: D Inputs DC 0 X 0 1 X 1 0 X DB 1 X 1 0 X 1 0 X DA 0 X 1 X 0 X Present StateNext State CBAC+B+A+ 000010 001XXX 010011 011101 100XXX 101110 110000 111XXX

19. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 19 Simplest Design Procedure: No remapping needed! DC = A DB = A C + B DA = B C Resulting Logic Level Implementation: 3 Gates, 8 Input Literals + Flipflop connections Using D Flipflops:

20. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 20 J-K Excitation Table Remapped Next State Functions Q+ = J Q + K Q Q0011Q0011 Q+ 0 1 0 1 J01XXJ01XX KXX10KXX10 Present State Next State Remapped Next State C00001111C00001111 B00110011B00110011 A01010101A01010101 C+ 0 X 0 1 X 1 0 X B+ 1 X 1 0 X 1 0 X A+ 0 X 1 X 0 X JC 0 X 0 1 X X X X KC X X 0 1 X JB 1 X X 1 X KB X 0 1 X X 1 X JA 0 X 1 X 0 X KA X X X 0 X 1 X Using J-K Flipflops:

21. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 21 Resulting Logic Level Implementation: 2 Gates, 10 Input Literals + Flipflop Connections Using J-K Flipflops:

22. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 22 Self-starting counters (cont’d) Re-deriving state transition table from don't care assignment 0101 A B C C+ 1 11101110 01010101 A B C B+ 0101010100 A B C A+ Present StateNext State CBAC+B+A+ 000010 001110 010011 011101 100010 101110 110000 111100 010 000110 101 011 001 111 100

23. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 23 Self-starting counters Start-up states  at power-up, counter may be in an unused or invalid state  designer must guarantee that it (eventually) enters a valid state Self-starting solution  design counter so that invalid states eventually transition to a valid state  may limit exploitation of don't cares implementation on previous slide 010 000110 101 011 001111 100 010 000110 101 011 001 111 100

24. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 24 Activity 2-bit up-down counter (2 inputs)  direction: D = 0 for up, D = 1 for down  count: C = 0 for hold, C = 1 for count 01 0011 10 C=0 D=X C=1 D=0 C=1 D=1 S1S0CDN1N0 000000 000100 001001 001111 010001 010101 011010 011100 100010 100110 101011 101101 110011 110111 111000 111110

25. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 25 Comparison of Mealy and Moore machines Mealy machines tend to have less states  different outputs on arcs (n 2 ) rather than states (n) Moore machines are safer to use  outputs change at clock edge (always one cycle later)  in Mealy machines, input change can cause output change as soon as logic is done – a big problem when two machines are interconnected – asynchronous feedback may occur if one isn’t careful Mealy machines react faster to inputs  react in same cycle – don't need to wait for clock  in Moore machines, more logic may be necessary to decode state into outputs – more gate delays after clock edge

26. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 26 Comparison of Mealy and Moore machines (cont’d) Moore Mealy Synchronous Mealy state feedback inputs outputsreg combinational logic for next state logic for outputs inputsoutputs state feedback reg combinational logic for next state logic for outputs inputsoutputs state feedback reg combinational logic for next state logic for outputs

27. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 27 D/1 E/1 B/0 A/0 C/0 1 0 0 0 0 1 1 1 1 0 reset currentnext resetinputstatestateoutput 1––A 00AB0 01AC0 00BB0 01BD0 00CE0 01CC0 00DE1 01DC1 00EB1 01ED1 Specifying outputs for a Moore machine Output is only function of state  specify in state bubble in state diagram  example: sequence detector for 01 or 10

28. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 28 currentnext resetinputstatestateoutput 1––A0 00AB0 01AC0 00BB0 01BC1 00CB1 01CC0 B A C 0/1 0/0 1/1 1/0 reset/0 Specifying outputs for a Mealy machine Output is function of state and inputs  specify output on transition arc between states  example: sequence detector for 01 or 10

29. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 29 Vending Machine FSM N D Reset Clock Open Coin Sensor Release Mechanism Example: vending machine Release item after 15 cents are deposited Single coin slot for dimes, nickels No change

30. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 30 Example: vending machine (cont’d) Suitable abstract representation  tabulate typical input sequences: 3 nickels nickel, dime dime, nickel two dimes  draw state diagram: inputs: N, D, reset output: open chute  assumptions: assume N and D asserted for one cycle each state has a self loop for N = D = 0 (no coin) S0 Reset S2 D S6 [open] D S4 [open] D S1 N S3 N S5 [open] N S8 [open] D S7 [open] N

31. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 31 Example: vending machine (cont’d) Minimize number of states - reuse states whenever possible symbolic state table presentinputsnextoutput stateDNstateopen 0¢00 0¢0 01 5¢0 1010¢0 11–– 5¢00 5¢0 0110¢0 1015¢0 11–– 10¢0010¢0 0115¢0 1015¢0 11–– 15¢––15¢1 0¢0¢ Reset 5¢5¢ N N N + D 10¢ D 15¢ [open] D

32. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 32 present stateinputsnext stateoutput Q1Q0DND1D0open 0000 000 01010 10100 11––– 0100 010 01100 10110 11––– 1000 100 01110 10110 11––– 11–– 111 Example: vending machine (cont’d) Uniquely encode states

33. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 33 D1 = Q1 + D + Q0 N D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D OPEN = Q1 Q0 Example: Moore implementation Mapping to logic 00110111XX1X111100110111XX1X1111 Q1 D1 Q0 N D 01101011XX1X011101101011XX1X0111 Q1 D0 Q0 N D 00100010XX1X001000100010XX1X0010 Q1 Open Q0 N D

34. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 34 present stateinputsnext stateoutput Q3Q2Q1Q0DND3D2D1D0open 00010000010 0100100 1001000 11----- 00100000100 0101000 1010000 11----- 01000001000 0110000 1010000 11----- 1000--10001 D0 = Q0 D’ N’ D1 = Q0 N + Q1 D’ N’ D2 = Q0 D + Q1 N + Q2 D’ N’ D3 = Q1 D + Q2 D + Q2 N + Q3 OPEN = Q3 Example: vending machine (cont’d) One-hot encoding

35. VII - Finite State Machines © Copyright 2004, Gaetano Borriello and Randy H. Katz 35 Equivalent Mealy and Moore state diagrams Moore machine  outputs associated with state 0¢ [0] 10¢ [0] 5¢ [0] 15¢ [1] N’ D’ + Reset D D N N+D N N’ D’ Reset’ N’ D’ Reset 0¢0¢ 10¢ 5¢5¢ 15¢ (N’ D’ + Reset)/0 D/0 D/1 N/0 N+D/1 N/0 N’ D’/0 Reset’/1 N’ D’/0 Reset/0 Mealy machine  outputs associated with transitions