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Some Slides from: U.C. Berkeley, U.C. Berkeley, Alan Mishchenko, Alan Mishchenko, Mike Miller, Mike Miller, Gaetano Borriello Gaetano Borriello Introduction.

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Presentation on theme: "Some Slides from: U.C. Berkeley, U.C. Berkeley, Alan Mishchenko, Alan Mishchenko, Mike Miller, Mike Miller, Gaetano Borriello Gaetano Borriello Introduction."— Presentation transcript:

1 Some Slides from: U.C. Berkeley, U.C. Berkeley, Alan Mishchenko, Alan Mishchenko, Mike Miller, Mike Miller, Gaetano Borriello Gaetano Borriello Introduction to Sequential Circuits

2 FSM (Finite State Machine) Optimization State tables State minimization State assignment Combinational logic optimization net-list identify and remove equivalent states assign unique binary code to each state use unassigned state-codes as don’t care

3 Sequential Circuits Sequential Circuits Sequential Circuits Primitive sequential elements Primitive sequential elements Combinational logic Combinational logic Models for representing sequential circuits Models for representing sequential circuits Finite-state machines (Moore and Mealy) Finite-state machines (Moore and Mealy) Representation of memory (states) Representation of memory (states) Changes in state (transitions) Changes in state (transitions) Basic sequential circuits Basic sequential circuits Shift registers Shift registers Counters Counters Design procedure Design procedure State diagrams State diagrams State transition table State transition table Next state functions Next state functions

4 State Assignment Choose bit vectors to assign to each “symbolic” state Choose bit vectors to assign to each “symbolic” state With n state bits for m states there are 2 n ! / (2 n – m)! state assignments [log n <= m <= 2 n ] With n state bits for m states there are 2 n ! / (2 n – m)! state assignments [log n <= m <= 2 n ] 2 n codes possible for 1st state, 2 n –1 for 2nd, 2 n –2 for 3rd, … 2 n codes possible for 1st state, 2 n –1 for 2nd, 2 n –2 for 3rd, … Huge number even for small values of n and m Huge number even for small values of n and m Intractable for state machines of any size Intractable for state machines of any size Heuristics are necessary for practical solutions Heuristics are necessary for practical solutions Optimize some metric for the combinational logic Optimize some metric for the combinational logic Size (amount of logic and number of FFs) Size (amount of logic and number of FFs) Speed (depth of logic and fanout) Speed (depth of logic and fanout) Dependencies (decomposition) Dependencies (decomposition)

5 State Assignment Strategies Possible Strategies Possible Strategies Sequential – just number states as they appear in the state table Sequential – just number states as they appear in the state table Random – pick random codes Random – pick random codes One-hot – use as many state bits as there are states (bit=1 –> state) One-hot – use as many state bits as there are states (bit=1 –> state) Output – use outputs to help encode states (counters) Output – use outputs to help encode states (counters) Heuristic – rules of thumb that seem to work in most cases Heuristic – rules of thumb that seem to work in most cases No guarantee of optimality – an problem No guarantee of optimality – an intractable problem

6 One-hot State Assignment Simple Simple Easy to encode, debug Easy to encode, debug Small Logic Functions Small Logic Functions Each state function requires only predecessor state bits as input Each state function requires only predecessor state bits as input Good for Programmable Devices Good for Programmable Devices Lots of flip-flops readily available Lots of flip-flops readily available Simple functions with small support (signals its dependent upon) Simple functions with small support (signals its dependent upon) Impractical for Large Machines Impractical for Large Machines Too many states require too many flip-flops Too many states require too many flip-flops Decompose FSMs into smaller pieces that can be one-hot encoded Decompose FSMs into smaller pieces that can be one-hot encoded Many Slight Variations to One-hot – “two hot” Many Slight Variations to One-hot – “two hot”

7 Heuristics for State Assignment Adjacent codes to states that share a common next state Adjacent codes to states that share a common next state Group 1's in next state map Group 1's in next state map Adjacent codes to states that share a common ancestor state Adjacent codes to states that share a common ancestor state Group 1's in next state map Group 1's in next state map Adjacent codes to states that have a common output behavior Adjacent codes to states that have a common output behavior Group 1's in output map Group 1's in output map

8 General Approach to Heuristic State Assignment All current methods are variants of this All current methods are variants of this 1) Determine which states “attract” each other (weighted pairs) 1) Determine which states “attract” each other (weighted pairs) 2) Generate constraints on codes (which should be in same cube) 2) Generate constraints on codes (which should be in same cube) 3) Place codes on Boolean cube so as to maximize constraints satisfied (weighted sum) 3) Place codes on Boolean cube so as to maximize constraints satisfied (weighted sum) Different weights make sense depending on whether we are optimizing for two-level or multi-level forms Different weights make sense depending on whether we are optimizing for two-level or multi-level forms Can't consider all possible embeddings of state clusters in Boolean cube Can't consider all possible embeddings of state clusters in Boolean cube Heuristics for ordering embedding Heuristics for ordering embedding To prune search for best embedding To prune search for best embedding Expand cube (more state bits) to satisfy more constraints Expand cube (more state bits) to satisfy more constraints

9 Output-Based Encoding Reuse outputs as state bits - use outputs to help distinguish states Reuse outputs as state bits - use outputs to help distinguish states Why create new functions for state bits when output can serve as well Why create new functions for state bits when output can serve as well Fits in nicely with synchronous Mealy implementations Fits in nicely with synchronous Mealy implementations

10 HG = ST’ H1’ H0’ F1 F0’ + ST H1 H0’ F1’ F0 HY = ST H1’ H0’ F1 F0’ + ST’ H1’ H0 F1 F0’ FG = ST H1’ H0 F1 F0’ + ST’ H1 H0’ F1’ F0’ HY = ST H1 H0’ F1’ F0’ + ST’ H1 H0’ F1’ F0 Output patterns are unique to states, we do not need ANY state bits – implement 5 functions (one for each output) instead of 7 (outputs plus 2 state bits) InputsPresent StateNext StateOutputs CTLTSSTHF 0––HGHG00010 –0–HGHG –HGHY10010 ––0HYHY00110 ––1HYFG –FGFG ––FGFY –1–FGFY ––0FYFY ––1FYHG Example of KISS Format

11 Current State Assignment Approaches For tight encodings using close to the minimum number of state bits For tight encodings using close to the minimum number of state bits Best of 10 random seems to be adequate (averages as well as heuristics) Best of 10 random seems to be adequate (averages as well as heuristics) Heuristic approaches are not even close to optimality Heuristic approaches are not even close to optimality Used in custom chip design Used in custom chip design One-hot encoding One-hot encoding Easy for small state machines Easy for small state machines Generates small equations with easy to estimate complexity Generates small equations with easy to estimate complexity Common in FPGAs and other programmable logic Common in FPGAs and other programmable logic Output-based encoding Output-based encoding Ad hoc - no tools Ad hoc - no tools Most common approach taken by human designers Most common approach taken by human designers Yields very small circuits for most FSMs Yields very small circuits for most FSMs

12 State Assignment = Various Methods Assign unique code to each state to produce logic-level description Assign unique code to each state to produce logic-level description utilize unassigned codes effectively as don’t cares utilize unassigned codes effectively as don’t cares Choice for S state machine Choice for S state machine minimum-bit encoding minimum-bit encoding log S log S maximum-bit encoding maximum-bit encoding one-hot encoding one-hot encoding using one bit per state using one bit per state something in between something in between Modern techniques Modern techniques hypercube embedding of face constraint derived for collections of states (Kiss,Nova) hypercube embedding of face constraint derived for collections of states (Kiss,Nova) adjacency embedding guided by weights derived between state pairs (Mustang) adjacency embedding guided by weights derived between state pairs (Mustang)

13 Hypercube Embedding Technique Observation : one -hot encoding is the easiest Observation : one -hot encoding is the easiest to decode to decode Am I in state 2,5,12 or 17? Am I in state 2,5,12 or 17? binary : x 4 ’x 3 ’x 2 ’x 1 x 0 ’(00010) + binary : x 4 ’x 3 ’x 2 ’x 1 x 0 ’(00010) + x 4 ’x 3 ’x 2 x 1 ’x 0 (00101) + x 4 ’x 3 ’x 2 x 1 ’x 0 (00101) + x 4 ’x 3 x 2 x 1 ’x 0 ’(01100) + x 4 ’x 3 x 2 x 1 ’x 0 ’(01100) + x 4 x 3 ’x 2 ’x1’x0 (10001) x 4 x 3 ’x 2 ’x1’x0 (10001) one hot : x 2 +x 5 +x 12 +x 17 one hot : x 2 +x 5 +x 12 +x 17 But one hot uses too many flip flops. But one hot uses too many flip flops. Exploit this observation Exploit this observation 1. two-level minimization after one hot 1. two-level minimization after one hot encoding identifies useful state group for encoding identifies useful state group for decoding decoding 2. assigning the states in each group to a single 2. assigning the states in each group to a single face of the hypercube allows a single product face of the hypercube allows a single product term to decode the group to states. term to decode the group to states.

14 FSM Optimization S2S2 S1S1 S3S Combinational Logic PIPO PS NS u1u1 u2u2 v1v1 v2v2 S4S4

15 State Group Identification Ex: state machine input current-state next state output input current-state next state output 0 start S start S S2 S S2 S S3 S S3 S S4 S S4 S S5 start 10 0 S5 start 10 0 S6 start 01 0 S6 start 01 0 S7 S S7 S start S start S S2 S S2 S S3 S S3 S S4 S S4 S S5 S S5 S S6 S S6 S S7 S S7 S6 00 Symbolic Implicant : represent a transition from one or more state to a next state under some input condition.

16 Representation of Symbolic Implicant Symbolic cover representation is related to a multiple-valued logic. Positional cube notation : a p multiple-valued logic is represented as P bits (V 1,V 2,...,V p ) (V 1,V 2,...,V p ) Ex: V = 4 for 5-value logic (00010) (00010) represent a set of values by one string represent a set of values by one string V = 2 or V = 4 V = 2 or V = 4 (01010) (01010)

17 Minimization of Multi-valued Logic Find a minimum multiple-valued-input cover - espresso Ex: A minimal multiple-valued-input cover

18 State Group Consider the first symbolic implicant This implicant shows that input “0” maps This implicant shows that input “0” maps “state-2” or “state-3” or “state-7” into “state-5” “state-2” or “state-3” or “state-7” into “state-5” and assert output “00” and assert output “00” This example shows the effect of symbolic logic minimization is to group together the states that are mapped by some input into the same next-state and assert the same output. This example shows the effect of symbolic logic minimization is to group together the states that are mapped by some input into the same next-state and assert the same output. We call it “state group” if we give encodings to We call it “state group” if we give encodings to the states in the state group in adjacent binary the states in the state group in adjacent binary logic and no other states in the group face, then the states group can be implemented as a cube. logic and no other states in the group face, then the states group can be implemented as a cube.

19 Group Face group face : the minimal dimension subspace containing the encoding assigned to that group. group face : the minimal dimension subspace containing the encoding assigned to that group. Ex: **0 group face Ex: **0 group face

20 Hyper-cube Embedding c a b state groups : {2,5,12,17} {2,6,17} wrong!

21 Hyper-cube Embedding c a b state groups : {2, 6, 17} {2, 4, 5} wrong! 617 6

22 Hyper-cube Embedding Advantage : Advantage : use two-level logic minimizer to identify good state group use two-level logic minimizer to identify good state group almost all of the advantage of one-hot encoding, but fewer state-bit almost all of the advantage of one-hot encoding, but fewer state-bit

23 Adjacency-Based State Assignment Basic algorithm: (1) Assign weight w(s,t) to each pair of states weight reflects desire of placing states weight reflects desire of placing states adjacent on the hypercube adjacent on the hypercube (2) Define cost function for assignment of codes to the states to the states penalize weights for the distance between the state codes penalize weights for the distance between the state codes eg. w(s,t) * distance(enc(s),enc(t)) eg. w(s,t) * distance(enc(s),enc(t)) (3) Find assignment of codes which minimize this cost function summed over all pairs of this cost function summed over all pairs of states. states. heuristic to find an initial solution heuristic to find an initial solution pair-wise interchange (simulated annealing) pair-wise interchange (simulated annealing) to improve solution to improve solution

24 Adjacency-Based State Assignment Mustang : weight assignment technique based on loosely maximizing common cube factors Mustang : weight assignment technique based on loosely maximizing common cube factors

25 How to Assign Weight to State Pair Assign weights to state pairs based on ability to extract a common-cube factor if these two states are adjacent on the hyper-cube. Assign weights to state pairs based on ability to extract a common-cube factor if these two states are adjacent on the hyper-cube.

26 Fan-Out-Oriented (examine present-state pairs) Present state pair transition to the same next state Present state pair transition to the same next state S1S1 S3S3 S2S2 $$$ S 1 S 2 $$$$ $$$ S 3 S 2 $$$$ Add n to w(S 1,S 3 ) because of S 2

27 Fan-Out-Oriented present states pair asserts the same output present states pair asserts the same output S2S2 S3S3 S1S1 S4S4 $/j Add 1 to w(S 1, S3) because of output j $$$ S 1 S 2 $$$1$ $$$ S 3 S 4 $$$1$

28 Fanin-Oriented (exam next state pair) The same present state causes transition to next state pair. The same present state causes transition to next state pair. $$$ S 1 S 2 $$$$ $$$ S 1 S 2 $$$$ $$$ S 1 S 4 $$$$ $$$ S 1 S 4 $$$$ Add n/2 to w(S 2,S 4 ) because of S 1 Add n/2 to w(S 2,S 4 ) because of S 1 S1S1 S2S2 S4S4

29 Fanin-Oriented (exam next state pair) The same input causes transition to next state pair. The same input causes transition to next state pair. $0$ S 1 S 2 $$$$ $0$ S 1 S 2 $$$$ $0$ S 3 S 4 $$$$ $0$ S 3 S 4 $$$$ Add 1 to w(S 2,S 4 ) because of input i Add 1 to w(S 2,S 4 ) because of input i ii S1S1 S3S3 S2S2 S4S4

30 Which Method Is Better? Which is better? Which is better? FSMs have no useful two-level FSMs have no useful two-level face constraints => adjacency-embedding FSMs have many two-level FSMs have many two-level face constraints => face-embedding

31 Summary Models for representing sequential circuits Models for representing sequential circuits Abstraction of sequential elements Abstraction of sequential elements Finite state machines and their state diagrams Finite state machines and their state diagrams Inputs/outputs Inputs/outputs Mealy, Moore, and synchronous Mealy machines Mealy, Moore, and synchronous Mealy machines Finite state machine design procedure Finite state machine design procedure Deriving state diagram Deriving state diagram Deriving state transition table Deriving state transition table Determining next state and output functions Determining next state and output functions Implementing combinational logic Implementing combinational logic Implementation of sequential logic Implementation of sequential logic State minimization State minimization State assignment State assignment Support in programmable logic devices Support in programmable logic devices

32 Some Tools History: Combinational Logic  single FSM  Hierarchy of FSM’s MISII Sequential Circuit Partitioning Facilities for managing networks of FSMs VIS (“handles” hierarchy) Sequential Circuit Optimization (single machine) SIS Facilities for handling latches


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