1. Chapter 6 Sequential Logic

2. Combinational circuit outputs depend on present inputs. Sequential circuit outputs depend on present inputs and the state of the memory elements. Combinational Circuit Memory Outputs Inputs Sequential Circuit Sequential Logic

3. Flip-Flop - a storage (memory) element. A flip-flop circuit has two outputs, one normal form and one complemented. It may have one or two inputs, depending on type. Clock, preset and clear functions may also be present. One flip-flop stores one binary bit. R Q S Q S R Q Q 1 0 0 0 1 0 0 1 0 0 0 1 1 1 0 0 X Y Z 0 0 1 0 1 0 1 0 0 1 1 0 NOR 1) Logic 1 on S sets Q to 1. 2) Logic 1 on R resets Q to 0. 3) Logic 1 on both S, R produce an indeterminate result.

4. Q S R Q ( T+1) 0 0 00 0 0 1 0 0 1 0 1 1 Indeterm 1 0 01 1 0 1 1 01 1 1 1 Indeterm Characteristic Table Q Q R CP S S Q CP R Q Clocked RS Flip-Flop When CLK = 1 S = 0, R=0Hold S= 0, R=1Q  0 S = 1, R = 0 Q  1 S = 1, R= 1not allowed

5. 0 0 d 1 1 0 d 1 S R SR Q Q Q(t + 1) = S + RQ SR= 0 SR must equal 0 so that S and R cannot both be 1 simultaneously Q = present state Q(t + 1) = next state Indeterminate states can be considered as don’t cares since either a 1 or a 0 may result after S and R both equal 1.

6. D CP S Q Q Q D Q(t+1) 0 0 0 0 1 1 1 0 0 1 1 1 Characteristic Table DQ CP Q 1 1 D Q Q( t + 1) = D D Flip-Flop When CLK = 0, the flip-flop holds When CLK = 1D qQ 0 00 0 10 1 01 1 11

7. Q Q K CP S R J JK Flip-Flop

8. J Q CP K Q Characteristic Table 0 0 1 1 1 0 0 1 J K Q Q(t+1) = J Q + KQ J K qQ(t+1) 0 0 00 0 0 11 0 1 00 0 1 10 1 0 01 1 0 11 1 1 01 1 1 1 0 Hold Reset Set Invert

9. Q Q T CP S R T Flip-Flop Invert T qQ(t+1) 0 00 0 11 1 01 1 10 Hold Characteristic Equation 1 Q 1 Q ( t + 1) = T Q + T Q TQ CP Q

10. * Synchronous: behavior can be defined from the knowledge of signals at discrete instants of time. A master clock is used, only change during a clock pulse. * Asynchronous: behavior depends on the order in which input signals change. Can be changed at any time. Level Triggering: Flip-Flop sensitive to pulse duration Edge Triggering: Flip-Flop sensitive to pulse transition (solves feedback timing problems) 1 0 Positive edge Negative edge Triggering of Flip-Flop

11. Master-Slave Flip-Flops: Contains two separate flip-flops S R S Q CP R Q Master S Q QR CP Slave Q Q

12. Problem: Instability occurs if output of memory elements (FF’s) are changing while output of combinational circuit that go to the Flip-Flop inputs are being sampled by the clock pulse. Inputs Output CP FF Comb. Logic Propagation delay from Flip-Flop input to output must be greater then clock pulse duration.

13. Input Output CP S Y Q Output state change occurs on the negative clock transition.

14. Mealy vs. Moore machines Control Logic Register (Flip-flops) Output Logic Inputs Outputs A collection of flip-flops is called a register. The value of the flip-flops defines the state of the machine. Mealy machine: The output is a function of the state of the machine and of the inputs. Moore machine: The output is a function only of the state of the machine. Moore = Output only a function of the state. Clock

15. A synchronous state machine Control Logic Register (Flip-flops) Output Logic Inputs Outputs Clock Presume all flip-flops are positive edge-triggered. 1) The controls are “captured” on the positive edge 2) It takes a little time (nS) for the flip-flops to settle to the new state 3) The new state affects the control logic 4) External inputs are changing, also affecting the control logic 5) The next positive edge occurs and the cycle repeats

16. State Transition Diagram The state transition diagram is a graphical representation of the machine changes from one state to another in reaction to the inputs. A state transition diagram is often the first step in the design of a synchronous state machine. State Name In/Out

17. A color sequence SSM Red Blue Gray Tan 0/0 0/1 1/1 0/0 1/0 Red /0 Blue /0 Gray /1 Tan /0 0 0 1 0 0 1 1 1 Mealy machine Moore machine

18. When is the output valid? Control Logic Register (Flip-flops) Output Logic Inputs Outputs Clock Since a Moore machine’s outputs are a function only of the state of the machine, its outputs are always valid except during transitions Since a Mealy machine’s outputs are a function of the state of the machine and the inputs, its outputs are valid only immediately after a transition. Most designs will latch (capture) the output of a Moore machine in an output register to provide them to the rest of the system.

19. Characterizing a SSM Red Blue Gray Tan 0/0 0/1 1/1 0/0 1/0 Red /0 Blue /0 Gray /1 Tan /0 0 0 1 0 0 1 1 1 Number of states: 4Number of flip-flops: 2 Number of inputs:Number of outputs: 11 Input = 0: Red-Blue-Gray-Tan-Red-… Input = 1: Red-Tan-Blue-Gray-Red-...

20. State Transition Table The state transition table is a tabular representation of the machine changes from one state to another in reaction to the inputs. The state transition table has the same information as the state transition diagram. Red Blue Gray Tan 0/0 0/1 1/1 0/0 1/0 Inputs define the columns States define the rows

21. J Q CP K Q Preset Clear PR CL Direct Inputs

22. State Diagrams State: The condition (values) stored in the flip-flops of a sequential circuit. Present State: The condition of the flip-flops prior to a clock pulse. Next State: Condition of the flip-flops after a clock pulse a d c b 1/0 1/1 0/1 1/0 0/0 1/0  state  transition between states which occurs with a clock pulse. X/Y  x= input which causes transition. y = output during present state.

23. Contains the same information as a state diagram Present state Next State X = 0 X = 1 Output X = 0 X = 1 a 0 0 c b00 b0 1 c b 10 c1 0 d c00 d1 1 c a01 In general, a state table for m flip-flops will have 2 m rows, one for each state. The next state and output section will have 2 n columns each for n inputs. External outputs can be taken from flip-flop output or from logic gates. If there are no logic gates for output, the output columns can be deleted. The output is then read directly from the present state of the flip-flops. State Table

24. Goal: reduce the number of flip-flops in a sequential circuit. Present state Next State X = 0 X = 1 Output X = 0 X = 1 a a b00 b c d 00 c a d00 d e f01 e a f01 f g f01 g a f01 Equivalent states = same input gives the same output for each state and the transitions go to the same state. In example above state g = state e..... State Reduction

25. ..... and state f = state d. Present state Next State X = 0 X = 1 Output X = 0 X = 1 a a b00 b c d 00 c a d00 d e f01 e a f01 f g f01 g a f01 State Reduction e

26. ..... and state f = state d. Present state Next State X = 0 X = 1 Output X = 0 X = 1 a a b00 b c d 00 c a d00 d e f01 e a f01 f g f01 g a f01 State Reduction e d d

27. State Assignment Some state assignment schemes can reduce the combinational portion of a sequential circuit. However, there are no state assignment techniques which guarantee minimization. Suggestion: 1) For counters use the sequence of binary numbers for state assignments. 2) Otherwise, make arbitrary assignments.

28. Characteristic tables define next state - when the input and present state are known. Excitation tables define the input conditions required to make a desired transition from a known present state to a a desired next state. Q S R Q ( T+1) 0 0 00 0 0 1 0 0 1 0 1 1 Indeterm 1 0 01 1 0 1 1 01 1 1 1 Indeterm SR Characteristic Table Q Q(t + 1) S R 0 0 0 d 0 1 1 0 1 0 0 1 1 1 d 0 SR Excitation Table Flip-Flop Excitation Tables

29. Q J K Q ( t+1) 0 0 0 0 1 0 0 1 0 1 1 1 1 0 0 1 1 0 1 1 0 1 1 1 1 0 JK Characteristic Table Q Q(t + 1) J K 0 0 0 d 0 1 1 d 1 0 d 1 1 1 d 0 JK Excitation Table Q D Q(t + 1) 0 0 0 0 1 1 1 0 0 1 1 1 D Characteristic Table Q Q(t + 1) D 0 0 0 0 1 1 1 0 0 1 1 1 D Excitation Table

30. Goal: obtain a logic diagram or list of Boolean functions which describe a sequential circuit meeting the design specification. 1) Write a word description. Draw a state diagram. 2) Construct a state table. 3) Perform state reduction. 4) Make state assignments. 5) Determine number of ff required and assign a letter to each. 6) Select type of ff to use. 7) Construct circuit excitation and output tables. 8) Reduce Boolean functions. 9) Draw the logic diagram. Sequential Design Process

31. Design a circuit to implement the following state diagram. a d c b 1/1 1/0 0/0 1/1 0/1 0/0 Example

32. 2) Conduct a state table. Present state Next State X = 0 X = 1 Output X = 0 X = 1 a a b11 b c b 01 c c d11 d d a00 3) Perform state reduction. None possible.

33. 4) Make state assignments. a = 0 0 b = 0 1 c = 1 0 d = 1 1 5) Determine number of flip-flops required 4 states required 2 flip-flops (2 n = 4) 6) Select flip-flop type. Choose T. (TA, TB)

34. 7) Construct excitation and output tables. Inputs of combinational circuit Output of combinational circuit Present State Input Next State FF inputsOutput A B X A B TA TB Z 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 0 0 1 1 0 1 1 1 0 1 1 1 1 0 1 1 0 0 0 1 1 1 0 0 1 1 0 aabbccddaabbccdd

35. Using: Q Q(t + 1) T 0 0 0 0 1 1 1 0 1 1 1 0 8) Reduce Boolean Functions. 0 0 0 1 0 0 1 0A B TA = A B X + A B X X

36. TB = B X + AX + A B X 0 1 0 1 1 0A B X 1 1 1 0 1 1 0 0A X B Z = B + A X

37. 9) Draw the logic diagram. T Q Q A B Q TA A A TB B B X Input Z Output Conbinational Circuit

38. ABXABX TA ABXABX TB Z BXBX AXAX AXAX B

39. Design a sequential circuit using the following state table: Present state Next State X = 0 X = 1 Output X = 0 X = 1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 0 0 1 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 1 1 3 flip-flop are requires for 5 states. There will be 3 numbered states (000, 110, 111). Letter the ff A,b, C. Construct an excitation table for RS ff. Example

40. Present StateInputNext StateFlip-Flop Inputs Output A B C X A B C S A R A S B R B S C R C Y 0 0 0 0 d d d d d d d d d d 0 0 0 1 d d d d d d d d d d 0 0 1 0 0 0 1 0 d 0 d d 0 0 0 0 1 1 0 1 0 0 d 1 0 0 1 0 0 1 0 0 0 1 1 0 d d 0 1 0 0 0 1 0 1 1 0 0 1 0 0 1 0 d 0 0 1 1 0 0 0 1 0 d 0 1 d 0 0 0 1 1 1 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 d 0 0 d 1 0 0 1 0 0 1 1 0 0 d 0 0 d 0 d 1 1 0 1 0 0 0 1 0 1 0 d d 0 0 1 0 1 1 1 0 0 d 0 0 d 0 1 1 1 1 0 0 d d d d d d d d d d 1 1 0 1 d d d d d d d d d d 1 1 1 0 d d d d d d d d d d 1 1 1 1 d d d d d d d d d d

41. Use the SR excitation table to complete the circuit excitation table: QQ(t +1) S R 0 0 0 d 0 1 1 0 1 0 0 1 1 1 d 0 Reduce Boolean function: B A C X d d 0 0 0 1 1 0 d d d d d d d 0 CX AB SA = BX

42. B A C X CX AB RA = CX d d d d d 0 0 d d d d d 0 0 0 1 Others SB = A B X RB = B C + B X S C = X R C = X Y = A X

43. Draw the logic diagram: S Q R Q A CP S Q R Q B CP S Q R Q B CP X Input Y Output SA RA SB RB SC RC CP A A B B C

44. Don’t Care States 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 1 1 1 0 0 0/0 1/0 1/1 ??

45. What about don’t care states? Self-Correcting: all unused states eventually lead to valid states. (some designs may specify self-correcting in one clock pulse.) Self-starting: initial state on power up is specified. Usually a master reset input is used. It is customary to provide a master- reset input whose purpose is to initialize the states of all flip-flops in the system. Typically, the master reset is a signal applied to all flip-flops asynchronously before master-reset signal, but some may be set to 1. Q: What if, because of a noise signal the circuit finds itself in an invalid state? In that case it is necessary to ensure that the circuit eventually goes into one of the valid states so it can resume normal operation. Don’t Care States

46. It was stated previously that unused states in a sequential circuit can be treated as don’t-care conditions. Once the circuit is designed, the m flip-flops in the system can be in any of 2 possible states. Some of these states were taken as don’t cares conditions. The circuit muse be investigated to determine the effect of these unused states. The next state from invalid sates can be determined. Don’t Care States

47. 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 1 1 1 0 0 0/0 1/0 1/1 0/0

48. 0 0 1 0 0 0 1 0 00 1 1 0 1 0 1/1 0/0 1/1 1/0 0/0 1/1 Design Problem

49. Example Problem: Design with T Flip-Flops 0 0 0 0 0 1 1 0 1 1 0 0 0 0 1 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 0 0 0 1 0 1 1 0 0 1 0 0 1 0 1 1 1 1 1 0 1 0 1 1 1 0 1 1 1 Present StateInputNext StateFlip-Flop Inputs Output A B C X A B C T A T B T C Unused States Need 3 Flip-Flops to Get 5 States

50. 0 0 1 0 0 0 1 0 00 1 1 0 1 0 1/1 0/0 1/1 1/0 0/0 1/1 Don’t Care States ?? 1 1 1 1 1 0 1 0 1

51. B A C X CX AB 0 1 1 0 0 0 0 0 d d d d 1 1 d d TA = A + BX B A C X CX AB 1 0 0 0 0 1 0 1 d d d d 1 1 d d T B = A + B C X + B C X + B C X A C X CX AB 1 0 1 0 0 0 1 0 d d d d 0 1 d d T C = AX + CX + A B C X A C X CX AB 0 1 1 0 d d d d 0 0 d d Z= AX

52. T Q Q T Q Q T Q Q Prob 6-20 CONTD A BXBX A B C X B X B C B X C AAAA X CXCX TCTC C C B A Z To Gates To Gates To Gates TBTB TATA X A *Note Clock Pulse is assumed

53. Prob CONTINUED Now, we must analyze circuit to confirm that unused states are in fact “Don’t Cares” Analyzes Procedure is: 1) Start w/Logic Diagram 2) Formulate FF input Equations 3) Derive next state equations using FF characteristics EQ. 4) Formulate transition table (state table w/binary #’s) 5) Formulate state diagram. 1) Logic Diagram on previous Page 2) T A = A + BXQ A = A T B = A + BC X + B C X + B C X Q B = B T C = AX + CX + A B C X Q C = C

54. 3) T F-F Char. EQ: Q(t +1) = TQ + TQ A = (A + B X) A + (A + BX) A A B X + [ A (B + X) ] A A B X + (A B + A X) A A B X B = (A + B C X + B C X + B C X) B + (A + B C X + B C X + B C X) B AB + B C X + [ A (B + C + X) (B + C + X) ( B + C + X) ] B AB + B C X + [ BA (B + BC + BX) (BC + BX) (BC + BX) ] AB + B C X + [B A + A B C + A B X) (BC + BX) (BC + BX) AB + B C X + [A B C + A B X + A B C + A B X + A B C X + A B X) (B C + B X) AB + B C X + A B C X + A B C X B = A B + A C X + A B C X A C CX AB 1 X B 1 1 1 1

55. C = (AX + CX + A B C X) C + ( A X + C X + A B C X) C A C X + A B C X +[ (A + X) (C + X) (A + B + C + X) ] C A C X + A B C X + (C A + C X) (C X) (C A + C B + C + C X) A C X + A B C X + ( C A X + CX) ( CA + CB + C + CX) A C X + A B C X + C A X B + C A X + C X A + C X B + CX A C X + A B C X + C A X ( B + 1) + C X A + C X B + C X A C X + A B C X + A C X + A CX + B C X + C X A C CX AB X B 1111 1 1 11 1 C = CX + A C X + A B X

56. 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 0 0 1 0 0 0 1 1 1 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 0 1 0 0 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 1 0 1 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 1 0 0 0 1 0 1 1 1 1 0 0 0 0 Present StateInputNext State Output A B C X A B C 4)

57. 5) 0 0 1 0 0 0 1 1 1 1 0 00 1 1 1 0 10 1 0 1 1 0 1/0 1/1 0/0 1/0 0/0 1/0 1/1 1/0 0/0 Unused state are “Don’t cares” since they all go to valid states. Other 5 states produce same state diagram as original. 0/0

58. Alternate way to get next states for “Don’t Cares” 0 1 1 0 0 0 d 12 d 13 d 15 d 14 1 1 d 11 d 10 1 0 0 0 0 1 d 12 d 13 d 15 d 14 1 1 d 11 d 10 TATA TBTB 1 0 1 0 0 0 1 0 d 12 d 13 d 15 d 14 0 1 d 11 d 10 TCTC 0 1 1 0 d 12 d 13 d 15 d 14 0 0 d 11 d 10 Z

59. PS Input NS Output ABC X A B C Z 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1

60. Example: Design a circuit to recognize this bit pattern: … 0 1 1 0 1 … When the position is recognized, return to a starting point (or points). Circuit should be self- starting and self - correcting. X Y = 1 when pattern is recognized Input pattern Sequential circuit

61. g h d e b b a c 1/0 0/0 1/1 1/0 0/0 1/0 0/0 0/1 a = 1’st digit = 0, correct b = 1’st digit = 1, incorrect c = 2’nd digit correct d = 3’rd digit correct e = 4’th digit correct f = all digits correct pattern recognized g = unused state. h = unused state.

62. Present State X = 0 X = 1 X = 1 X = 0 A B C A B C A B C Y Y Next State Output a 0 0 0 0 0 0 0 1 0 0 0 b 0 0 0 0 0 0 0 0 1 0 0 c 0 1 0 0 0 0 0 1 1 0 0 d 0 1 1 1 0 0 0 0 1 0 0 e 1 0 0 0 0 0 1 0 0 0 0 f 1 0 1 0 0 0 0 0 1 1 1 g 1 1 0 0 0 0 0 0 1 0 0 k 1 1 1 0 0 0 0 0 1 0 0 Date reduction shows b, g, h as equivalent states; however, 3 flip-flops are still required. Implement the circuit with JK flip-flops.

63. Q Q(t+1) J K 0 0 0 d 0 1 1 d 1 0 d 1 1 1 d 0

64. Present StateInputNext StateFlip-Flop Inputs Output A B C X A B C J A K A J B K B J C K C Y 0 0 0 0 0 0 0 0 d 0 d 0 d 0 0 0 0 1 0 1 0 0 d 1 d 0 d 0 0 0 1 0 0 0 0 0 d 0 d d 1 0 0 0 1 1 0 0 1 0 d 0 d d 0 0 0 1 0 0 0 0 0 0 d d 1 0 d 0 0 1 0 1 0 1 1 0 d d 0 1 d 0 0 1 1 0 1 0 0 1 d d 1 d 1 0 0 1 1 1 0 0 1 0 d d 1 d 0 0 1 0 0 0 0 0 0 d 1 0 d 0 d 0 1 0 0 1 1 0 1 d 0 0 d 1 d 0 1 0 1 0 0 0 0 d 1 0 d d 1 1 1 0 1 1 0 0 1 d 1 0 d d 0 1 1 1 0 0 0 0 0 d 1 d 1 0 d 0 1 1 0 1 0 0 1 d 1 d 1 1 d 0 1 1 1 0 0 0 0 d 1 d 1 d 1 0 1 1 1 1 0 0 1 d 1 d 1 d 0 0

65. A C B d d d d 1 X A C B X 1 1 1 1 1 KA= B + C + X A C B d d d d 1 X JB = A C X A C B d d d d X 1 1 1 1 KB= B + C + X 1 1 1

66. A C B 1 d d X JC = BX + AX d 1 d d A C B d d X KC = X d d 1 d d 1 1 1 A C B X 1 Y = ABC

67. J Q K Q A CP J Q K Q A CP J Q K Q A CP cp A A B BY C C CP X

68. A Clocked sequential circuit has 2 inputs, X 1, and X 2, and one output, Z. The output should equal 1 if and only if the inputs agree and have agreed for an even non-zero (2,4,6, …) number of clock pulses since the last pulse when they disagreed. Convert the two inputs into a single input, D, that equals 1 when X 1 & X 2 disagree. X1X1 X2X2 d Z CLK

69. A B 1/0 0/0 0/1 2 states: How many F-F? (1) 0 0 1 0 1 d 0 1 0 0 0 d 1 0 0 1 d 1 1 1 0 0 d 1 A Input A Output FF Inputs NS 1 0 d J = D 1 0 d K = 1 D A D A 1 0 d K = AD D A J Q K Q A CP cp X1X2X1X2 Z 1

70. Prepare a state diagram for a sequential circuit whose output, Z, equals 1 if and only if input sequence has either 1001 or 11 as its most recent subsequence. AB DC 1/1 0/0 1/0 0/0 1/0 0/0 1/1 One’s 1&0 1 & 0 & 0

71. A single-input, single-output clocked sequential circuit is to produce an output of 1 coincident with a Ø - input, provided that the Ø - input is immediately preceded by at least two consecutive 1-inputs AC B 0/0 0/1 1/0 0/0 1/0 A = 00 B = 01 C = 10 PS Input NS Outputs A B X A B JA KA JB KB Z 0 0 0 0 0 0 d 0 d Ø 0 0 1 0 1 0 d 1 d Ø 0 1 0 0 0 0 d d 1 0 0 1 1 1 0 1 d d 1 0 1 0 0 0 0 d 1 0 d 1 1 0 1 1 0 d 0 0 d 0 1 1 0 d d d d d d d 1 1 1 d d d d d d d

72. A B 0 0 1 0 d d A B 1 0 d d d d A 0 0 d d 0 1 d d JA= BX KA = X B X KB = 1 A 1 0 d d 0 0 B X Z = AX

73. B J Q K B A J Q K B1

74. Try different state assignment: PS Input NS Outputs A B X A B JA KA JB KB Z 1 1 0 1 1 d 0 d 0 0 1 1 1 0 1 d 1 d 0 0 0 1 0 1 1 1 d d 0 0 0 1 1 0 0 0 d d 1 0 0 0 0 1 1 1 d 1 d 1 0 0 1 0 0 0 d 0 d 0 1 0 0 d d d d d d d 1 0 1 d d d d d d d A d d 0 1 1 0 d d JA= X X A 0 1 d d KA = X X d d BB

75. A JB = X X 1 0 d d B A 0 0 1 0 KB =BX X d d B Z=AX B J Q K B A J Q K B X

76. State Equations Sometimes called “Next-State Equations” - A(t + 1) = (AB + AB + AB)X + Abx Next State of a F-F Boolean Functions specifying present state condition that make the next state of the Flip-Flop be 1. (that is, if this function = 1, the next clock pulse will cause the output, 1, of the flip-flop to be 1] - Can be derived from a State Table or Logic Diagram - State equations plus output function(s) fully specify a sequential circuit.

77. State Equation Derivation - From a state table: Next StateOutput Present State x = 0 x = 1 x = 0 x = 1 AB AB AB y y 0 0 0 0 0 1 0 0 0 1 1 1 0 1 0 0 1 0 1 0 0 0 0 1 1 1 1 0 1 1 0 0

78. Read off next-state columns for A, Alternating from input Ø to input 1 and put directly into K-Map 1 1 1 1 0 0 0 1 1 1 1 0 0 1 A 1 0 1 A 11 1 A( t + 1) = Bx’ + (B + x’) A = Bx’ + (Bx’)’ A a) B( t + 1) = A’x + (A’ + x) B = Ax + (Ax’)’ B a) Form of Rs flip-flop: q(t + 1) = S + R Q

79. State Equation Derivation - Form a logic Diagram: R Q’ S Q R Q’ S Q 1 2 3 4 x’ A x A’ x B’ x’ B A A’ B B’ CP

80. - For flip - flop B: R = AX S = A X -Substitute into RS F-F characteristic equation: Q(t + 1) = S + RQ Gives B(t + 1) = Ax + (Ax) B (which is same as got with state table derivation)

81. Use of state Equations - Have to use when doing analyses, such as checking validity of design that used “Don’t Cares” - Convenient for design when circuit is alrady specified in this form or when the equations are easily derived from the state table. -- Easy eith D flip-flops -- Sometimes convenient with JK flip-flops -- Possible with RS and T flip-flops but requires considerable algebraic manipulation.

82. State Reduction: Another Method PS NS Output X=0 X=1 A d c 0 b f h 0 c e d 1 d a e 0 ec a 1 ff b 0 gb h 1 hc g 1

83. b c d e f g h d- f c -h a b c d e f g - Go thru & set up a table - If intersection of too states is at an “x”, they cannot be equal; Put an x in that block. - Continue passes thru table until nothing left to cross out - Blocks with no X reflect equal States. Example: a  b iff d  f and c  h a  c because outputs differ