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1 Latches & Flip-flops Computer Architecture CS 215.

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1 1 Latches & Flip-flops Computer Architecture CS 215

2 2 Sequential Circuits  Storage elements Latches or Flip- Flops  Combinatorial Logic Combinat ional Logic Storage Elements Inputs Outputs State Next State

3 3 Sequential Circuits  Combinatorial Logic Next state function Next State = f(Inputs, State) Output function (Mealy) Outputs = g(Inputs, State) Output function (Moore) Outputs = h(State)  Output function type depends on specification and affects the design significantly Combinat ional Logic Storage Elements Inputs Outputs State Next State

4 4 Sequential Circuits  Synchronous Behavior defined from knowledge of its signals at discrete instances of time Storage elements observe inputs and can change state only in relation to a timing signal (clock pulses from a clock)  Asynchronous Behavior defined from knowledge of inputs an any instant of time and the order in continuous time in which inputs change If clock just regarded as another input, all circuits are asynchronous! Nevertheless, the synchronous abstraction makes complex designs tractable!

5 5 Discrete Event Simulation  Rules: Gates modeled by an ideal (instantaneous) function and a fixed gate delay Any change in input values is evaluated to see if it causes a change in output value Changes in output values are scheduled for the fixed gate delay after the input change At the time for a scheduled output change, the output value is changed along with any inputs it drives

6 6 Simulated NAND Gate  Example: A 2-Input NAND gate with a 0.5 ns. delay  Assume A and B have been 1 for a long time  At time t=0, A changes back to 1. to a 0 at t= 0.8 ns, F A B DELAY 0.5 ns. F(Instantaneous)

7 7 Basic (NAND) S–R Latch  “Cross- Coupling” two NAND gates gives the S-R Latch  S = 0, R = 0 is forbidden as input pattern Q S (set) R (reset) Q 1101Now Q “remembers” Both go high 11??Unstable! Time

8 8 Basic (NOR) S–R Latch  Cross- coupling two NOR gates gives the S – R Latch S (set) R (reset) Q Q

9 9 Clocked S-R Latch  Adding two NAND gates to the basic S-R NAND latch gives the clocked S–R latch:  Has a time sequence behavior similar to the basic S-R latch except that the S and R inputs are only observed when the line C is high.  C means “control” or “clock”. S R Q C Q

10 10 Clocked S-R Latch  The Clocked S-R Latch can be described by a table  The table describes what happens after the clock [at time (t+1)] based on: current inputs (S,R) and current state Q(t). S R Q Q C

11 11 D Latch  Adding an inverter to the S-R Latch, gives the D Latch:  Note that there are no “indeterminate” states! Q D Q(t+1) Comment No change Set Q Clear Q No Change C D Q Q D Q C Q

12 12 Flip-Flops  Master-slave flip-flop  Edge-triggered flip-flop  Standard symbols for storage elements

13 13  Two clocked S-R latches in series with the clock on the second latch inverted  The input is observed by the first latch with C = 1  The output is changed by the second latch with C = 0  The path from input to output is broken by the difference in clocking values (C = 1 and C = 0).  The behavior demonstrated by the example with D driven by Y given previously is prevented since the clock must change from 1 to 0 before a change in Y based on D can occur. C S R Q Q C R Q Q C S R Q S Q S-R Master-Slave Flip-Flop

14 14 Edge-Triggered D Flip-Flop  The edge-triggered D flip-flop is the same as the master- slave D flip-flop  It can be formed by: Replacing the first clocked S-R latch with a clocked D latch or Adding a D input and inverter to a master-slave S-R flip-flop  The delay of the S-R master-slave flip-flop can be avoided since the 1s-catching behavior is not present with D replacing S and R inputs  The change of the D flip-flop output is associated with the negative edge at the end of the pulse  It is called a negative-edge triggered flip-flop C S R Q Q C Q Q C D Q D Q

15 15 Positive-Edge Triggered D Flip-Flop  Formed by adding inverter to clock input  Q changes to the value on D applied at the positive clock edge within timing constraints to be specified  Our choice as the standard flip-flop for most sequential circuits C S R Q Q C Q Q C D Q D Q

16 16  Master-Slave: Postponed output indicators  Edge-Triggered: Dynamic indicator Standard Symbols for Storage Elements

17 17 State Diagrams  The sequential circuit function can be represented in graphical form as a state diagram with the following components: A circle with the state name in it for each state A directed arc from the Present State to the Next State for each state transition A label on each directed arc with the Input values which causes the state transition, and A label:  On each circle with the output value produced, or  On each directed arc with the output value produced.

18 18 State Diagrams  Label form: On circle with output included:  state/output  Moore type output depends only on state On directed arc with the output included:  input/output  Mealy type output depends on state and input

19 State Diagram: SR Latch 19

20 20 Other Flip-Flop Types  J-K and T flip-flops Behavior Implementation  Basic descriptors for understanding and using different flip-flop types Characteristic tables Characteristic equations Excitation tables  For actual use, see Reading Supplement - Design and Analysis Using J-K and T Flip-Flops

21 21 J-K Flip-flop  Behavior Same as S-R flip-flop with J analogous to S and K analogous to R Except that J = K = 1 is allowed, and For J = K = 1, the flip-flop changes to the opposite state As a master-slave, has same “1s catching” behavior as S-R flip-flop If the master changes to the wrong state, that state will be passed to the slave  E.g., if master falsely set by J = 1, K = 1 cannot reset it during the current clock cycle

22 22 J-K Flip-flop  Implementation To avoid 1s catching behavior, one solution used is to use an edge- triggered D as the core of the flip- flop D C K J J C K Q = 0 Q = 1 JK=00 JK=10 or 11 JK=01 or 11 Build this!

23 23 T Flip-flop  Behavior Has a single input T  For T = 0, no change to state  For T = 1, changes to opposite state  Same as a J-K flip-flop with J = K = T  As a master-slave, has same “1s catching” behavior as J-K flip-flop  Cannot be initialized to a known state using the T input Reset (asynchronous or synchronous) essential

24 24 T Flip-flop  Implementation To avoid 1s catching behavior, one solution used is to use an edge- triggered D as the core of the flip- flop C D T T C Q = 0 Q = 1 T=0 T = 1 Build this!

25 25 Basic Flip-Flop Descriptors  Used in analysis Characteristic table - defines the next state of the flip-flop in terms of flip-flop inputs and current state Characteristic equation - defines the next state of the flip-flop as a Boolean function of the flip-flop inputs and the current state  Used in design Excitation table - defines the flip-flop input variable values as function of the current state and next state

26 26 D Flip-Flop Descriptors  Characteristic Table  Characteristic Equation Q(t+1) = D  Excitation Table D 0 1 Operation Reset Set 0 1 Q(t1) + Q(t+1) D Operation Reset Set

27 27 T Flip-Flop Descriptors  Characteristic Table  Characteristic Equation Q(t+1) = T  Q  Excitation Table Q(t + 1) Q(t) 1 0 T No change Complement Operation Q(t) No change Complement Operation 0 1 TQ(t1) Q(t) Q(t) +

28 28 S-R Flip-Flop Descriptors  Characteristic Table  Characteristic Equation Q(t+1) = S + R Q, S. R = 0  Excitation Table Operation No change Set Reset No change S X Q(t+ 1) Q(t) R X OperationS R No change Reset Set Undefined 0 1 ? Q(t+1) Q(t)

29 29 J-K Flip-Flop Descriptors  Characteristic Table  Characteristic Equation Q(t+1) = J Q + K Q  Excitation Table No change Set Reset Complement OperationJ K 0 1 Q(t +1) Q(t) Q(t) Q(t + 1) Q(t) Operation X X 0 1 K 0 1 X X J No change Set Reset No Change


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