2Sequential Circuits Storage elements Combinatorial Logic Inputs CombinationalLogicStorage ElementsInputsOutputsStateNextStorage elementsLatches or Flip-FlopsCombinatorial Logic
3Sequential Circuits Inputs Outputs Combinational Logic Storage ElementsInputsOutputsStateNextCombinatorial LogicNext state function Next State = f(Inputs, State)Output function (Mealy) Outputs = g(Inputs, State)Output function (Moore) Outputs = h(State)Output function type depends on specification and affects the design significantly
4Sequential Circuits Synchronous Asynchronous Behavior defined from knowledge of its signals at discrete instances of timeStorage elements observe inputs and can change state only in relation to a timing signal (clock pulses from a clock)AsynchronousBehavior defined from knowledge of inputs an any instant of time and the order in continuous time in which inputs changeIf clock just regarded as another input, all circuits are asynchronous!Nevertheless, the synchronous abstraction makes complex designs tractable!
5Discrete Event Simulation Rules:Gates modeled by an ideal (instantaneous) function and a fixed gate delayAny change in input values is evaluated to see if it causes a change in output valueChanges in output values are scheduled for the fixed gate delay after the input changeAt the time for a scheduled output change, the output value is changed along with any inputs it drives
6Simulated NAND Gate t (ns) A B F(I) F Comment – 1 Example: A 2-Input NAND gate with a 0.5 ns. delayAssume A and B have been 1 for a long timeAt time t=0, A changes back to 1. to a 0 at t= 0.8 ns,FABDELAY 0.5 ns.F(Instantaneous)t (ns)ABF(I)FComment–1A=B=1 for a long timeÞÜF(I) changes to 10.5F changes to 1 after a 0.5 ns delay0.8F(Instantaneous) changes to 00.13F changes to 0 after a 0.5 ns delay
7Basic (NAND) S–R LatchS (set)“Cross-Coupling” two NAND gates gives the S-R LatchS = 0, R = 0 is forbidden as input patternQQR (reset)TimeRSQComment1?Stored state unknown“Set” Q to 1Now Q “remembers” 1“Reset” Q to 0111Now Q “remembers” 011Both go high11??Unstable!
8Basic (NOR) S–R LatchS (set)R (reset)QCross-coupling two NOR gates gives the S – R LatchRSQComment?Stored state unknown1“Set” Q to 1Now Q “remembers” 1“Reset” Q to 0Now Q “remembers” 0Both go lowUnstable!Time
9Clocked S-R LatchAdding two NAND gates to the basic S-R NAND latch gives the clocked S–R latch:Has a time sequence behavior similar to the basic S-R latch except that the S and R inputs are only observed when the line C is high.C means “control” or “clock”.SRQC
10Clocked S-R Latch The Clocked S-R Latch can be described by a table The table describes what happens after the clock [at time (t+1)] based on:current inputs (S,R) andcurrent state Q(t).SRQC
11D Latch Adding an inverter to the S-R Latch, gives the D Latch: QCAdding an inverter to the S-R Latch, gives the D Latch:Note that there are no “indeterminate” states!QDQ(t+1)CommentNo change1Set QClear QNo ChangeCDQ
12Flip-Flops Master-slave flip-flop Edge-triggered flip-flop Standard symbols for storage elements
13S-R Master-Slave Flip-Flop CSRQTwo clocked S-R latches in series with the clock on the second latch invertedThe input is observed by the first latch with C = 1The output is changed by the second latch with C = 0The path from input to output is broken by the difference in clocking values (C = 1 and C = 0).The behavior demonstrated by the example with D driven by Y given previously is prevented since the clock must change from 1 to 0 before a change in Y based on D can occur.
14Edge-Triggered D Flip-Flop CSRQDThe edge-triggered D flip-flop is the same as the master- slave D flip-flopIt can be formed by:Replacing the first clocked S-R latch with a clocked D latch orAdding a D input and inverter to a master-slave S-R flip-flopThe delay of the S-R master-slave flip-flop can be avoided since the 1s-catching behavior is not present with D replacing S and R inputsThe change of the D flip-flop output is associated with the negative edge at the end of the pulseIt is called a negative-edge triggered flip-flop
15Positive-Edge Triggered D Flip-Flop Formed by adding inverter to clock inputQ changes to the value on D applied at the positive clock edge within timing constraints to be specifiedOur choice as the standard flip-flop for most sequential circuitsCSRQD
16Standard Symbols for Storage Elements Master-Slave: Postponed output indicatorsEdge-Triggered: Dynamic indicator(a) LatchesSRSRD with 0 ControlDCD with 1 Control(b) Master-Slave Flip-FlopsTriggered DTriggered SR(c) Edge-Triggered Flip-Flops
17State DiagramsThe sequential circuit function can be represented in graphical form as a state diagram with the following components:A circle with the state name in it for each stateA directed arc from the Present State to the Next State for each state transitionA label on each directed arc with the Input values which causes the state transition, andA label:On each circle with the output value produced, orOn each directed arc with the output value produced.
18State Diagrams Label form: On circle with output included: state/outputMoore type output depends only on stateOn directed arc with the output included:input/outputMealy type output depends on state and input
20Other Flip-Flop Types J-K and T flip-flops BehaviorImplementationBasic descriptors for understanding and using different flip-flop typesCharacteristic tablesCharacteristic equationsExcitation tablesFor actual use, see Reading Supplement - Design and Analysis Using J-K and T Flip-Flops
21J-K Flip-flop Behavior Same as S-R flip-flop with J analogous to S and K analogous to RExcept that J = K = 1 is allowed, andFor J = K = 1, the flip-flop changes to the opposite stateAs a master-slave, has same “1s catching” behavior as S-R flip-flopIf the master changes to the wrong state, that state will be passed to the slaveE.g., if master falsely set by J = 1, K = 1 cannot reset it during the current clock cycle
22J-K Flip-flop Build this! J C K JK=10 or 11 JK=00 D J Q = 0 Q = 1 K C ImplementationTo avoid 1s catching behavior, one solution used is to use an edge-triggered D as the core of the flip-flopJCKBuild this!DCKJQ = 0Q = 1JK=00JK=10 or 11JK=01 or 11
23T Flip-flop Behavior Same as a J-K flip-flop with J = K = T Has a single input TFor T = 0, no change to stateFor T = 1, changes to opposite stateSame as a J-K flip-flop with J = K = TAs a master-slave, has same “1s catching” behavior as J-K flip-flopCannot be initialized to a known state using the T inputReset (asynchronous or synchronous) essential
24T Flip-flop Build this! T C T = 1 T=0 D T Q = 0 Q = 1 C Implementation To avoid 1s catching behavior, one solution used is to use an edge-triggered D as the core of the flip-flopTCBuild this!Q = 0Q = 1T=0T = 1CDT
25Basic Flip-Flop Descriptors Used in analysisCharacteristic table - defines the next state of the flip-flop in terms of flip-flop inputs and current stateCharacteristic equation - defines the next state of the flip-flop as a Boolean function of the flip-flop inputs and the current stateUsed in designExcitation table - defines the flip-flop input variable values as function of the current state and next state