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Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 1 / 60 Sequential Circuits Combinational Circuit Memory Elements Inputs Outputs Asynchronous Synchronous Combinational Circuit Flip-flops Inputs Outputs Clock

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 2 / 60 Latches SR Latch S R Q 0 QQ’ 0 0 0 0 1 0 0 01 Q = Q 0 Initial Value

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 3 / 60 Latches SR Latch S R Q 0 Q Q’ 0 0 001 0 0 1 1 0 0 0 10Q = Q 0

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 4 / 60 Latches SR Latch S R Q 0 Q Q’ 0 0 001 0 0 110 0 1 00 0 1 1 0 1 Q = 0 Q = Q 0

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 5 / 60 Latches SR Latch S R Q 0 Q Q’ 0 0 001 0 0 110 0 1 001 0 1 1 1 0 1 0 01 Q = 0 Q = Q 0 Q = 0

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 6 / 60 Latches SR Latch S R Q 0 Q Q’ 0 0 001 0 0 110 0 1 001 0 1 101 1 0 0 0 1 0 1 10 Q = 0 Q = Q 0 Q = 1

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 7 / 60 Latches SR Latch S R Q 0 Q Q’ 0 0 001 0 0 110 0 1 001 0 1 101 1 0 010 1 0 1 1 0 0 1 10 Q = 0 Q = Q 0 Q = 1

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 8 / 60 Latches SR Latch S R Q 0 Q Q’ 0 0 001 0 0 110 0 1 001 0 1 101 1 0 010 1 0 110 1 1 0 0 1 1 1 00 Q = 0 Q = Q 0 Q = 1 Q = Q’ 0

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 9 / 60 Latches SR Latch S R Q 0 Q Q’ 0 0 001 0 0 110 0 1 001 0 1 101 1 0 010 1 0 110 1 1 000 1 1 1 1 0 1 1 00 Q = 0 Q = Q 0 Q = 1 Q = Q’ 0

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 10 / 60 Latches SR Latch S RQ 0 Q0Q0 0 10 1 01 1 Q=Q’=0 No change Reset Set Invalid S R Q 0 Q=Q’=1 0 11 1 00 1 Q0Q0 Invalid Set Reset No change

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 11 / 60 Latches SR Latch S RQ 0 Q0Q0 0 10 1 01 1 Q=Q’=0 No change Reset Set Invalid S’ R’Q 0 Q=Q’=1 0 11 1 00 1 Q0Q0 Invalid Set Reset No change

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 12 / 60 Controlled Latches SR Latch with Control Input C S RQ 0 x x Q0Q0 1 0 0 Q0Q0 1 0 10 1 1 01 1 1 1Q=Q’Q=Q’ No change Reset Set Invalid

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 13 / 60 Controlled Latches D Latch (D = Data) C DQ 0 x Q0Q0 1 00 1 1 No change Reset Set C Timing Diagram D Q t Output may change

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 14 / 60 Controlled Latches D Latch (D = Data) C DQ 0 x Q0Q0 1 00 1 1 No change Reset Set C Timing Diagram D Q Output may change

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 15 / 60 Flip-Flops Controlled latches are level-triggered Flip-Flops are edge-triggered C CLKPositive Edge CLKNegative Edge

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 16 / 60 Flip-Flops Master-Slave D Flip-Flop D Latch (Master) DCDC Q D Latch (Slave) DCDC QQD CLK D Q Master Q Slave Looks like it is negative edge-triggered MasterSlave

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 17 / 60 Flip-Flops Edge-Triggered D Flip-Flop DQ Q DQ Q Positive Edge Negative Edge

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 18 / 60 Flip-Flops JK Flip-Flop JQ QK D = JQ’ + K’Q

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 19 / 60 Flip-Flops T Flip-Flop D = TQ’ + T’Q = T Q JQ Q K T DQ Q T D = JQ’ + K’Q TQ Q

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 20 / 60 Flip-Flop Characteristic Tables DQ Q DQ(t+1) 00 11 Reset Set JKQ(t+1) 00Q(t)Q(t) 010 101 11Q’(t) No change Reset Set Toggle JQ QK TQ Q TQ(t+1) 0Q(t)Q(t) 1Q’(t) No change Toggle

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 21 / 60 Flip-Flop Characteristic Equations DQ Q DQ(t+1) 00 11 Q(t+1) = D JKQ(t+1) 00Q(t)Q(t) 010 101 11Q’(t) Q(t+1) = JQ’ + K’Q JQ QK TQ Q TQ(t+1) 0Q(t)Q(t) 1Q’(t) Q(t+1) = T Q

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 22 / 60 Flip-Flop Characteristic Equations Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) 0000 0011 010 011 100 101 110 111 No change Reset Set Toggle

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 23 / 60 Flip-Flop Characteristic Equations Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) 0000 0011 0100 0110 100 101 110 111 No change Reset Set Toggle

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 24 / 60 Flip-Flop Characteristic Equations Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) 0000 0011 0100 0110 1001 1011 110 111 No change Reset Set Toggle

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 25 / 60 Flip-Flop Characteristic Equations Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) 0000 0011 0100 0110 1001 1011 1101 1110 No change Reset Set Toggle

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 26 / 60 Flip-Flop Characteristic Equations Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) 0000 0011 0100 0110 1001 1011 1101 1110 K 0100 J1101 Q Q(t+1) = JQ’ + K’Q

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 27 / 60 Flip-Flops with Direct Inputs Asynchronous Reset DQ Q R Reset R’DCLKQ(t+1) 0xx0

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 28 / 60 Flip-Flops with Direct Inputs Asynchronous Reset DQ Q R Reset R’DCLKQ(t+1) 0xx0 10 ↑ 0 11 ↑ 1

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 29 / 60 Flip-Flops with Direct Inputs Asynchronous Preset and Clear PR’CLR’DCLKQ(t+1) 10xx0 DQ Q CLR Reset PR Preset

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 30 / 60 Flip-Flops with Direct Inputs Asynchronous Preset and Clear PR’CLR’DCLKQ(t+1) 10xx0 01x x 1 DQ Q CLR Reset PR Preset

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 31 / 60 Flip-Flops with Direct Inputs Asynchronous Preset and Clear PR’CLR’DCLKQ(t+1) 10xx0 01x x 1 110 ↑ 0 111 ↑ 1 DQ Q CLR Reset PR Preset

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 32 / 60 Analysis of Clocked Sequential Circuits The State ●State = Values of all Flip-Flops Example A B = 0 0

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 33 / 60 Analysis of Clocked Sequential Circuits State Equations A(t+1) = D A = A(t) x(t)+B(t) x(t) = A x + B x B(t+1) = D B = A’(t) x(t) = A’ x y(t) = [A(t)+ B(t)] x’(t) = (A + B) x’

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 34 / 60 Analysis of Clocked Sequential Circuits State Table (Transition Table) A(t+1) = A x + B x B(t+1) = A’ x y(t) = (A + B) x’ Present State Input Next State Output ABxABy 000 001 010 011 100 101 110 111 t+1 t t 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 1 1 0 0

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 35 / 60 Analysis of Clocked Sequential Circuits State Table (Transition Table) A(t+1) = A x + B x B(t+1) = A’ x y(t) = (A + B) x’ Present State Next StateOutput x = 0x = 1x = 0x = 1 ABABAB yy 00000100 01001110 10001010 11001010 t+1 t t

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 36 / 60 Analysis of Clocked Sequential Circuits State Diagram 0 1 0 0 11 0/00/0 0/10/1 1/01/0 1/01/0 1/01/0 1/01/00/10/1 0/10/1 AB input/output Present State Next StateOutput x = 0x = 1x = 0x = 1 ABABAB yy 00000100 01001110 10001010 11001010

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 37 / 60 Analysis of Clocked Sequential Circuits D Flip-Flops Example: DQ Q x CLK y A Present State Input Next State AxyA 000 001 010 011 100 101 110 111 0 1 1 0 1 0 0 1 01 00,11 01,10 A(t+1) = D A = A x y

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 38 / 60 Analysis of Clocked Sequential Circuits JK Flip-Flops Example: J A = BK A = B x’ J B = x’K B = A x A(t+1) = J A Q’ A + K’ A Q A = A’B + AB’ + Ax B(t+1) = J B Q’ B + K’ B Q B = B’x’ + ABx + A’Bx’ Present State I/P Next State Flip-Flop Inputs ABxABJAJA KAKA JBJB KBKB 000 001 010 011 100 101 110 111 0 0 1 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 1 1 0 0 1 1 1 0 0 0 0 1 0 1 1 0 1 1 0 0 1

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 39 / 60 Analysis of Clocked Sequential Circuits JK Flip-Flops Example: Present State I/P Next State Flip-Flop Inputs ABxABJAJA KAKA JBJB KBKB 000 001 010 011 100 101 110 111 0 0 1 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 1 1 0 0 1 1 1 0 0 0 0 1 0 1 1 0 1 1 0 0 1 0 1 0 11 0 101 0 1 0 0 1

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 40 / 60 Analysis of Clocked Sequential Circuits T Flip-Flops Example: T A = B xT B = x y = A B A(t+1) = T A Q’ A + T’ A Q A = AB’ + Ax’ + A’Bx B(t+1) = T B Q’ B + T’ B Q B = x B Present State I/P Next State F.F Inputs O/P ABxABTATA TBTB y 000 001 010 011 100 101 110 111 0 0 1 0 1 0 0 1 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 1 1

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 41 / 60 Analysis of Clocked Sequential Circuits T Flip-Flops Example: Present State I/P Next State F.F Inputs O/P ABxABTATA TBTB y 000 001 010 011 100 101 110 111 0 0 1 0 1 0 0 1 0 1 0 0 1 1 0 1 0 0000001100000011 0 1 1 1 0 0/00/0 1/01/0 0/00/0 1/01/0 1/01/0 1/11/1 0/00/0 0/10/1

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 42 / 60 Mealy and Moore Models Present State I/P Next State O/P ABxABy 000000 001010 010001 011110 100001 101100 110001 111100 Mealy state outputinput For the same state, the output changes with the input Present State I/P Next State O/P ABxABy 000000 001010 010010 011100 100100 101110 110111 111001 Moore state outputinput For the same state, the output does not change with the input

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 43 / 60 Moore State Diagram State / Output 0 0 / 00 1 / 0 1 1 / 11 0 / 0 0 1 1 1 00 0 1

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 44 / 60 Timing Diagram 0 0 / 00 1 / 0 1 1 / 11 0 / 0 00 1 1 0 0 1 1 CLK State A B y x No effect 0000 0101 1010 0000 0101 0101 A B xy

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 45 / 60 Timing Diagram 0 0 1 1 1 0 0/0 1/0 1/1 0/0 1/1 1/0 CLK State A B y x 1010 A B xy

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 46 / 60 Design of Clocked Sequential Circuits Example: Detect 3 or more consecutive 1’s S0 / 0S0 / 0S 1 / 0 S 3 / 1S 2 / 0 0 1 1 0 0 1 0 1 StateA B S0S0 0 S1S1 0 1 S2S2 1 0 S3S3 1

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 47 / 60 Design of Clocked Sequential Circuits Example: Detect 3 or more consecutive 1’s Present State Input Next State Output ABxABy 000 001 010 011 100 101 110 111 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 S0 / 0S0 / 0S 1 / 0 S 3 / 1S 2 / 0 0 1 1 0 0 1 0 1

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 48 / 60 Design of Clocked Sequential Circuits Example: Detect 3 or more consecutive 1’s Present State Input Next State Output ABxABy 000 001 010 011 100 101 110 111 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 A(t+1) = D A (A, B, x) = ∑ (3, 5, 7) B(t+1) = D B (A, B, x) = ∑ (1, 5, 7) y (A, B, x) = ∑ (6, 7) D Synthesis using D Flip-Flops

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 49 / 60 Design of Clocked Sequential Circuits with D F.F. Example: Detect 3 or more consecutive 1’s D A (A, B, x) = ∑ (3, 5, 7) = A x + B x D B (A, B, x) = ∑ (1, 5, 7) = A x + B’ x y (A, B, x) = ∑ (6, 7) = A B D Synthesis using D Flip-Flops B 0010 A0110 x B 0100 A0110 x B 0000 A0011 x

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 50 / 60 Design of Clocked Sequential Circuits with D F.F. Example: Detect 3 or more consecutive 1’s D A = A x + B x D B = A x + B’ x y = A B D Synthesis using D Flip-Flops

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 51 / 60 Flip-Flop Excitation Tables Present State Next State F.F. Input Q(t)Q(t)Q(t+1)D 00 01 10 11 Present State Next State F.F. Input Q(t)Q(t)Q(t+1)JK 00 01 10 11 0 0 (No change) 0 1 (Reset) 0 x 1 x x 1 x 0 0 1 0 1 1 0 (Set) 1 1 (Toggle) 0 1 (Reset) 1 1 (Toggle) 0 0 (No change) 1 0 (Set) Q(t)Q(t)Q(t+1)T 00 01 10 11 0 1 1 0

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 52 / 60 Design of Clocked Sequential Circuits with JK F.F. Example: Detect 3 or more consecutive 1’s Present State Input Next State Flip-Flop Inputs ABxAB JAJA KAKA JBJB KBKB 00000 00101 01000 01110 10000 10111 11000 11111 0 x 1 x x 1 x 0 x 1 x 0 J A (A, B, x) = ∑ (3) d JA (A, B, x) = ∑ (4,5,6,7) K A (A, B, x) = ∑ (4, 6) d KA (A, B, x) = ∑ (0,1,2,3) J B (A, B, x) = ∑ (1, 5) d JB (A, B, x) = ∑ (2,3,6,7) K B (A, B, x) = ∑ (2, 3, 6) d KB (A, B, x) = ∑ (0,1,4,5) JK Synthesis using JK F.F. 0 x 1 x x 1 0 x 1 x x 1 x 0

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 53 / 60 Design of Clocked Sequential Circuits with JK F.F. Example: Detect 3 or more consecutive 1’s J A = B xK A = x’ J B = xK B = A’ + x’ JK Synthesis using JK Flip-Flops B 0010 Axxxx x B xxxx A1001 x B 01xx A01xx x B xx11 Axx01 x

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 54 / 60 Design of Clocked Sequential Circuits with T F.F. Example: Detect 3 or more consecutive 1’s Present State Input Next State F.F. Input ABxABT A T B 00000 00101 01000 01110 10000 10111 11000 11111 0 0 0 1 1 0 1 0 T Synthesis using T Flip-Flops 0 1 1 1 0 1 1 0 T A (A, B, x) = ∑ (3, 4, 6) T B (A, B, x) = ∑ (1, 2, 3, 5, 6)

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 55 / 60 Design of Clocked Sequential Circuits with T F.F. Example: Detect 3 or more consecutive 1’s T A = A x’ + A’ B x T B = A’ B + B x T Synthesis using T Flip-Flops B 0010 A1001 x B 0111 A0101 x

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 56 / 60 Homework Mano ●Chapter 5 ♦ 5-1 ♦ 5-3 ♦ 5-6 ♦ 5-8 ♦ 5-9

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 57 / 60 Homework 5-1The D latch is constructed with four NAND gates and an inverter. Consider the following three other ways for obtaining a D latch. In each case, draw the logic diagram and verify the circuit operation. (a) Use NOR gates for the SR latch part and AND gates for the other two. An inverter may be needed. (b) Use NOR gates for all four gates. Inverters may be needed. (c) Use four NAND gates only (without an inverter). This can be done by connecting the output of the upper gate that goes to the SR latch to the input of the lower gate instead of the inverter output.

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 58 / 60 Homework 5-3Show that the characteristic equation for the complement output of a JK flip-flop is Q’(t+1) = J’Q + K Q 5-6A sequential circuit with two D flip-flops, A and B; two inputs, x and y; and one output, z, is specified by the following next-state and output equations: A(t+1) = x’ y + x A B(t+1) = x’ B + x A z = B (a) Draw the logic diagram of the circuit. (b) List the state table for the sequential circuit. (c) Draw the corresponding state diagram.

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 59 / 60 Homework 5-8Derive the state table and the state diagram of the sequential shown circuit. Explain the function that the circuit performs.

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept. 60 / 60 Homework 5-9A sequential circuit has two JK flip-flops A and B and one input x. The circuit is described by the following flip-flop input equations: J A = x K A = B’ J B = x K B = A (a) Derive the state equations A(t+1) and B(t+1) by substituting the input equations for the J and K variables. (b) Draw the state diagram of the circuit.

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