1 Overall Roadmap Technology Characteristics (ORTC) 2012 For ITRS San Francisco Mascone Center Thursday, 7/12/121-3:30pm ITRS Public Conference Tracks[Final Rev 6 - includes only Backup I]ITRS Front End of Line Technologies - TechXPOT South, 1-3:30pmORTC – Alan AllanITRS Back End of Line Technologies - TechXPOT North, 1-3:30pmORTC – Bob DoeringITRS CrossCut Technologies - Extreme Electronics Stage, South Hall, 2-3:30pmORTC – Paolo Gargini
2 ITRS Public Conference Thursday, 07/12/12 ITRS CrossCut Technologies (Extreme Electronics Stage, South Hall, 2:00pm-3:30pm)2:00-2:05Greeting from the ITRS IRC ChairIRC Session Chair from Korea2:05-2:20Overall Roadmap Technology Characteristics (ORTC)IRC member – Paolo Gargini2:20-2:35Factory integrationGopal Rao2:35-2:50Environment, safety, and HealthLeo Kenny2:50-3:05MetrologyAlain Diebold3:05-3:20Yield enhancement (YE)Lothar Pfitzner3:20-3:25Q and A3:25-3:30Closing remarksIRC Session ChairITRS Front End of Line Technologies - TechXPOT South (1:00pm-3:30pm)1:00-1:05Greeting from the ITRS IRC ChairIRC Session Chair from Taiwan—Carlos Diaz1:05-1:20Overall Roadmap Technology Characteristics (ORTC)IRC member – Alan Allan1:20-1:35System driversJuan-antonio Carballo1:35-1:50DesignAndrew Kahng1:50-2:05Modeling and simulationJuergen Lorenz2:05-2:20Process integration, devices, and structures (PIDS)Kwok Ng2:20-2:35LithographyMark Neisser2:35-2:50Front end processes (FEP)Mike Walden2:50-3:05Emerging research devices (ERD)Victor Zhirnov3:05-3:20Emerging research materials (ERM)Michael Garner3:20-3:25Q and A3:25-3:30Closing remarksIRC Session ChairITRS Back End of Line Technologies TechXPOT North (1:00pm-3:30pm)1:00-1:05Greeting from the ITRS IRC ChairIRC Session Chair from Japan-Hidemi Ishiuchi1:05-1:20Overall Roadmap Technology Characteristics (ORTC)IRC member – Bob Doering1:20-1:40More than MooreIRC member from Europe1:40-1:55InterconnectPaul Zimmerman1:55-2:10Assembly and packagingBill Bottoms2:10-2:25Test and Test EquipmentRoger Barth2:25-2:40Micro-electro-mechanical systems (MEMS)Michael Gaitan2:40-2:55RF and analog/mixed-signal technologies (RFAMS)Jack Pekarik2:55-3:00Q and A3:00-3:15Closing RemarksIRC Session Chair
3 2012 Update ITRS ORTC Technology Trend Summary Unchanged for 2012: MPU contacted M11) 2-year cycle trend through 2013 [27nm (“14nm” node)]; then 3-year trend to 202660f2 SRAM 6t cell Design Factor175f2 Logic Gate 4t Design Factor2) Unchanged for 2012 Tables: MPU Functions/Chip and Chip Size ModelsDesign TWG Model for Chip Size and Density Model trends – tied to technology cycle timing trends and cell design factorsORTC line item OverHead (OH) area model, includes non-active areaUnchanged for 2012 Tables: MPU GLpr, GLph – trends “smoothed” by 2011 PIDS modeling4) Unchanged for 2012 Tables: Max Chip Frequency trends (reset in 2011 to 3.6Ghz/2010 plus 4% CAGR trend)Unchanged for 2012 Tables: Vdd High Performance, Low operating and standby line items from 2011 PIDS model track “smoothed” gate length changesNote: See PIDS tables for 2012 Update to be released at end of 2012 for impact due to acceleration of MugFET and FDSOI “Equivalent Scaling” timing into 2012
4 2012 Update ITRS ORTC Technology Trend Summary (cont.) Unchanged for 2012 Tables: DRAM contacted M1:One-year M1 accelerationNew for 2012: 4f2 one-year delay to 20147) Unchanged for 2012 Tables: Flash Un-contacted Poly:2+-year pull-in of Poly; however slower 4-year cycle (0.5x per 8yrs) trend to 2020/10nm; then 3-year trend to 2022/8nm; then Flat Poly after 2022/8nmand 3bits/cell extended to 2018; 4bits/cell delay to 2022Unchanged for 2012 Tables: DRAM Bits/Chip and Chip Size Model:3-year generation “Moore’s Law” bits/chip doubling cycle target (1-2yr delay for smaller chip sizes <30mm2 – 2x/2.5yrs)Unchanged for 2012 Tables: Flash Bits/Chip and Chip Size Model:3-year generation “Moore’s Law” bits/chip doubling cycle target (after 1-yr acceleration; then 1-2Tbits; keep chip size <160mm2)3D on-chip bit layers with relaxed half-pitch tradeoffs are included for maximum bits per chipNew 2012 Update Survey Emphasis: layer range from 8/32nm -128/18nm Layers to 16/48nm – 256/24nm Layers (option C in 2011 ORTC Table 2)
5 2012 Update ITRS ORTC Technology Trend Summary (cont.) 10) Unchanged for 2012 Tables: ORTC Table 5 - Litho # of Mask Counts MPU, DRAM,Flash Survey inputs Unchanged for 2012IC Knowledge (ICK) model contribution extends mask levels range to 2024Possible 2012 Update consideration: update ICK model to 2011 Mask Counts (only YE impacted)11) Unchanged for 2012 Update: IRC 450mm Timing Graphic Position:Timing Status to be reviewed with G450C in July, 2012)Consortia work underwayIDM and Foundry Pilot lines: ;Production: [corrected early target in 2012 Update]G450C Consortium continues good progress on 450mm program activities to meet the ITRS Timing1) Consortium operations are using 450mm early test wafer process, metrology and patterning capability to support Supplier development193 immersion multiple exposure litho tools are under development to support consortium and manufacturers’ schedules for target “1xnm technology” goal450mm increasing silicon demand is needed from consortium demonstrations to support development3) Europe Position Unchanged – EEMI450 status was reviewed with IRC in Netherlands Apr’124) 300mm wafer generation in parallel line item header with 450mm;Including Technology upgrade assumptionsAssuming compatibility of 300mm productivity extensions into the 450mm generation;ITRS-based ICK Strategic Model commercially available and updated to 2011 ITRS, including 300mm and 450mm Range Scenarios for silicon and equipment demand12) Unchanged for 2012 Update: More than Moore white paper online atMtM Workshop completed in Netherlands, in April and reviewed at Summer ITRS meetingEurope workshop included new iNEMI applications presentation (Grace O’Malley/Europe iNEMI Mgr. – highlights on Automotive; Medical; Energy; Lighting; et al)ITRS MEMS TWG and Chapter cross-roadmap work underway for 2013 iNEMI Roadmap
6 2013 Renewal Preparation ITRS ORTC Technology Trend Summary (cont.) Technology Pacing Cross-TWG Study Group (CTSG) 2012 work underway to preparation for 2013 ITRS Renewal (kickoff Dec’12), including:IRC Equivalent Scaling Graphic UpdateProposals for timing placement of MuGFET, FDSOI, and III/V Ge Timing; now based on one IDM or Foundry company, who may lead technology production rampDesign and FEP Logic Technology TrendsMonitor and Update MPU and Leading Edge Logic technology trends, includingOngoing- evaluate alignment of “nodes” with latest M1 industry statusConsider High Performance vs. Low Power transistor type needsConsider extending 2yr cycle to 2017/14nm (”7nm” node)Functions/Chip and Chip Size Models tbd; based on final consensus of new proposalsOn-Chip Frequency Proposals – Align with PIDS modeling and evaluate/update to industry trendsPIDS and FEP Memory Survey Proposal UpdatesMonitor and Update DRAM and Flash technology trendsLitho and FEP (and PIDS and Design) Survey for CD Variability and ControlMonitor and Update Litho and Etch Gpr/Gph Ratio for CD control trendsA&P/Design Power (Thermal) ModelDevelop proposals for Power Dissipation "hot spot" model rather than chip area basisPIDS/Design Max On-chip Frequency vs Intrinsic ModelingTargeted for 8% (vs. 13%) CAGR (1/CV/I) intrinsic transistor performance (to align with 2011 ITRS 4% Design Frequency trend)Consider Intrinsic Transistor and Ring Oscillator model ChangesIncluding MASTAR static modeling near-term and TCAD dynamic long-term modelingIncluding “equivalent scaling” tradeoffs (FDSOI, MuGFET, III-V/Ge) with dimensional scalingYE Defect Density ModelingUpdate ORTC Defect Density model work to latest Litho Mask Count Model – still seeking defect modeling resources support
7 Figure 4 The Concept of Moore’s Law and More More than Moore: DiversificationMore Moore: MiniaturizationCombining SoC and SiP: Higher Value SystemsBaseline CMOS: CPU, Memory, LogicBiochipsSensorsActuators[e.g. MEMS]HVPowerAnalog/RFPassives130nm90nm65nm45nm32nm22nm16 nm.VInformationProcessingDigital contentSystem-on-chip(SoC)Beyond CMOSInteracting with people and environmentNon-digital contentSystem-in-package(SiP)Source: ITRS - Exec. Summary Fig. 4
8 Production Ramp-up Model and Technology/Cycle Timing Figure 2a- (within an established wafer generation*)- *see also Figure 2a for ERD/ERM Research and PIDS Transfer timing; and also- Figure 6 (450mm topic) for Typical Wafer Generation Pilot and Production “Ramp Curves”Production Ramp-up Model and Technology/Cycle Timing2012 UpdateNote:Fewer leadingIDM CompaniesRequiresAdaption ofDefinitionTo allow oneIDM CompanyOr a FoundryRepresentingMany FablessCompaniesTo Lead aTechnologyProductionRamp TimingMonths-24AlphaTool1224-12DevelopmentProductionBetaPre-ProductionFirstConf.PapersFirst 1-2 CompaniesReachingCombined Production2202002K20K200KAdditionalLead-time:ERD/ERMResearch andPIDS TransferVolume (Wafers/Month)ProductionSource: ITRS - Exec. Summary Fig. 2aWork in Progress - Do Not Publish
9 Source: 2011 ITRS - Exec. Summary Fig. 2b; plus: Figure 2b A Typical Technology Production “Ramp” Curve for ERD/ERM Research and PIDS Transfer timing- including an example for III/V Hi-Mobility Channel Technology Timing Scenario- Acceleration to 2015 Scenario for the 2012 Update workMonthsAlphaToolDevelopmentProductionBetaPre-Volume (Wafers/Month)2202002K20K200KResearch-7224-48-24-96Transfer to PIDS/FEP(96-72moLeadtime)FirstTech. Conf.Device PapersUp to ~12yrsPrior to Product201920172015201320112021Hi-m ChannelExample:1st 1-2 Co’sReachProductCircuits PapersUp to ~ 5yrsHi-m Channel Proposal - for 2013 ITRS workProductionSource: ITRS - Exec. Summary Fig. 2b; plus:[http://www.eetimes.com/electronics-news/ /Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-option ]
10 2012 ITRS Update* 450mm Production Ramp-up Model [ 2011 ITRS Executive Summary Fig. 6 - A Typical Wafer Generation Pilot Line and Production “Ramp” Curve]VolumeYearsAlphaToolBetaSilicon is supporting development using partially-patterned and processed test wafers IDM & Foundry Pilot LinesManufacturingDemonstrations focus on xnm M1 half-pitch capable toolsDevelopmentProductionIncreasing450mm Silicon DemandFrom DemonstrationsPre-Production< Consortium Demonstration2010201120122015201620132014Production*Note: the IRC recommended updating the ITRS 450mm Timing Graphic for use in the 2011 ITRS Special Topic and 2012 UpdateRoadmap guidance; based on SEMATECH guidanceSource: ITRS - Executive Summary Fig. 6
11 Backup I – Final Rev 5First (1-10) foils – Public ORTC for Thursday, 7/12 in S.Francisco;Including Backup I (11-24) Foils for the Public Conference(12) ORTC Fig. 3 Memory Trends(13) ORTC Fig. 4 MPU Trends(14) ORTC Fig. 4 MPU Trends with Memory Trends Overlay(15) ORTC Fig. 4 MPU Trends with Memory Trends and Equivalent Scaling Trends Overlay(16) ORTC Fig. 5 Equivalent Scaling Trends Overlay with Leading Company PIDS 2012 ITRS Timing(17) ORTC Fig. 5 Equivalent Scaling Trends Overlay with Fast Follower and 2013 ITRS Timing(18) ORTC Fig. 6 Function Sizes in 2012 ITRS Timing(19) ORTC Fig. 7 Memory Moore’s Law Functions/Chip and Chip Sizes in 2012 ITRS Timing(20) ORTC Fig. 8 MPU Moore’s Law Functions/Chip and Chip Sizes in 2012 ITRS Timing(21) ORTC Table 1 plus 2013 ITRS considerations(22) SICAS Capacity analysis update(23,24) DRAM and Flash Functions/Chip 2009 ITRS vs ITRS (2 foils)
13 Logic (MPU and high-performance ASIC) Half Pitch and Gate Length 2011 ITRS Figure 4 Unchanged for 2012 – ORTC Table 1 Graphical Trends –Logic (MPU and high-performance ASIC) Half Pitch and Gate Length2013 CTSGWORK; UpdateProposals tobe consideredLong-Term ’19-’2616nmSource: ITRS - Executive Summary Fig 4
14 Logic (MPU and high-performance ASIC) Half Pitch and Gate Length 2011 ITRS Figure 4 Unchanged for 2012 – ORTC Table 1 Graphical Trends –Logic (MPU and high-performance ASIC) Half Pitch and Gate Length[ MPUvs. MemoryHalf-Pitches ]Long-Term ’19-’2616nmFlash TrendsDRAM TrendsSource: ITRS - Executive Summary Fig 4
15 M1 pace extension to 2017 ; then 3yrs again 2011 ITRS Figure 4 Unchanged for 2012 – ORTC Table 1 Graphical Trends –Logic (MPU and high-performance ASIC) Half Pitch and Gate Length[ MPUIncluding PIDSMugFET and FDSOIAcceleration]Long-Term ’19-’2616nm2012 ITRS Update Unchanged: “22nm” (ITRS 2011 Planar M1=38nm ; GL=24nm);3-year Logic M1 Technology Pace after 20132-yearM1 pace extension to ; then 3yrs again[ also includingMemoryHalf-PitchesCartoon trendsFor comparison ]Flash TrendsDRAM Trends2013 ITRS Work Consider: “7nm” pull-in to 2017 (from ITRS 2011 Planar M1=14nm/’19)?;III/V Ge pull-in to 2015?; ITRS GLph = 11.7nm unchanged?;Logic and Flash (3yr cycle) both drive Lithography after 2017; Logic M1 after 2022?MuG-FETFDSOIHi-u,(tbd)Source: ITRS - Executive Summary Fig 4
16 Sub-Team Transistor Modeling Work Underway for UPDATED06/24/12FOR IRC and2012 CTSGWORKAnd 2013 ITRSPreparation2011 ITRS Figure 5 “Equivalent Scaling” Roadmap for Logic (MPU and high performance ASIC)Figure 5 ORTC Table 1 Graphical Trends (including overlay of 2009 industry logic “nodes” and ITRS trendsfor comparison); also including proposals for MugFET and FDSOI (2012) ITRS acceleration[ PIDS/FEP/DesignHP/LOP/LSTPSub-Team Transistor Modeling Work Underway for2013 ITRS ]MetalHigh kGate-stack material20092012201520182021BulkFDSOIMulti-gate(on bulk or SOI)Structure (electrostatic control)Channelmaterial2nd generationSi + StressSDHigh-µInGaAs; GePDSOInth generationPossibleDelayPossible Pull -in1668nm45nm32nm22nm16nm2011 ITRS DRAM M1 :2011 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm nm nmMPU/hpASIC “Node”: “45nm” “32nm” “22/20nm” “16/14nm” “11/10nm” “8/7nm”2011 ITRS hi-perf GLph : nm 29nm 29nm 27nm 24nm 22nm 20nm nm nm2011 ITRS hi-perf GLpr : nm 47nm 47nm 41nm 35nm 31nm 28nm nm nm11nm2011 ITRS Flash Poly :54nm2011 ITWG Table Timing:PIDS Acceleration - for 2012 ITRS Update22-248nm202415nm450mm1st Production2012 UpdateNote:LeadershipcompanyFirst Manu-facturingcould setmoreAggressivefirstproductiontarget,since“fastfollowers”may trail1-3 yearsSource: ITRS - Executive Summary Fig 5
17 Source: 2011 ITRS - Executive Summary Fig 5 2011 ITRS Figure 5 “Equivalent Scaling” Roadmap for Logic (MPU and high performance ASIC)Figure 5 ORTC Table 1 Graphical Trends (including overlay of 2009 industry logic “nodes” and ITRS trendsfor comparison); also including proposals for MugFET and FDSOI (2012) and III/V Ge (2013) ITRS accelerationMetalHigh kGate-stack material20092012201520182021BulkFDSOIMulti-gate(on bulk or SOI)Structure (electrostatic control)Channelmaterial2nd generationSi + StressSDHigh-µInGaAs; GePDSOInth generationPossibleDelayPossible Pull -in1768nm45nm32nm22nm16nm2011 ITRS DRAM M1 :2011 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm nm nmMPU/hpASIC “Node”: “45nm” “32nm” “22/20nm” “16nm/14nm” “11/10nm” “8/7nm”2011 ITRS hi-perf GLph : nm 29nm 29nm 27nm 24nm 22nm 20nm nm nm2011 ITRS hi-perf GLpr : nm 47nm 47nm 41nm 35nm 31nm 28nm nm nm11nm2011 ITRS Flash Poly :54nm2011 ITWG Table Timing:PIDS Acceleration - for 2012 ITRS Update22-248nm202415nmProposal - for 2013 ITRS prep.MPU =DRAM2015 onM1 2-yrCycle?MPU <2017 onFDSOI MugFET pull-in to “14nm”/2014?“…IBM will move to finFETs based on silicon-on-insulator wafers at the 14 nm node….”“…You don’t need well contacts. And anyone who does a cost analysis will conclude that the cost of isolation in bulk is comparable to the cost of the SOI wafer…”“…IBM has developed an embedded DRAM technology on its current SOI platform, he said carrying eDRAM forward to vertical transistors will be relatively straightforward…”“…The Fishkill Alliance of companies, including Samsung, GlobalFoundries, Toshiba, and others, will pursue bulk finFETs at the 14nm node…”MPU/hpASIC “Node”(nm): “45” “38” “32” “27” “22.5” “19” “16” “13.4” “11.25” “9.5” “8.0” “6.7” “5.6” “4.73” “4.0” “3.34” “2.81” “2.37” “2.0”2011 ITWG Table Timing:2-year “Node” Cycle /2yrs = /yr2011 ITRS M1 2yr cyc(nm):2011 ITRS M1 3yr cyc (nm):Multiple companies with Bulk MugFET pull-in to “14nm”/2014?2012 UpdateNote:LeadershipcompanyFirst Manu-facturingcould setmoreAggressivefirstproductiontarget,since“fastfollowers”may trail1-3 years?UPDATED06/24/12FOR IRC and2012 CTSGWORKAnd 2013 ITRSPreparation
18 Product Function Size Trends Unchanged; except 4f2 moved to 2014 2011 ORTC Figure 6Product Function Size Trends Unchanged; except 4f2 moved to 2014PIDS NAND Flash Multi-Layer 3D Modelvs. “Slower” Poly half-pitch Dimensional Reduction Rate affects 3D Bit size & density (not graphed)Long-Term ’19-’262011 ITRS:Updated06/24/12FOR 2012 CTSGWORK[transistor + capacitor]Source: ITRS - Executive Summary Fig 6MPU/ASICAlignmentDesign TWGActual SRAM [60f2]& Logic Gate [175f2]DRAM4f2AddedWAS:Begin in2011IS: DelayedTo 2013 ‘14Flash [4f2]1) 2-yr CycleExtended to 2010;2) 3 bits/cell added[andextended to 2026in the 2011 ITRS];3) 4 bits/cell movedfrom 2012 [to 2021in the 2011 ITRS]3D - 8 layers3D layers3D -16layers/48nm?3D -256layers/24nm?4-yr cycle?5.5-yr cycleFlash Impact of:Vs:
19 Figure ITRS Product Technology Trends: Memory Product Functions/Chip and Industry Average “Moore’s Law” and Chip Size Trends [unchanged for the 2012 Update]Long-Term ’19-’262011 ITRS:20114Tbits Possible with PIDS NAND Flash Multi-Layer 3D Model Scenario OptionDRAM4f2AddedWAS:Begin in2013IS: DelayedTo 2013 ‘143D layers/ ‘252025/32nm/3bits/cell4Tbits =128x33Gbits2025/18nm/3bits/cell13Tbits =128x99GbitsSource: ITRS - Executive Summary Fig 7
20 [unchanged for 2012 Update] Figure ITRS Product Technology Trends: MPU Product Functions/Chip and Industry Average “Moore’s Law” and Chip Size Trends[unchanged for 2012 Update]<260mm2<140mm2MPU= 2x/3yrs= 2x/2yrsAverage "Moore's Law" = 2x/2yrsLong-Term ’19-’262011 ITRS:2011ITRS:Unchanged, but Extend edTransistors/chip& Chip SizeModelsto 2026On 3-yearCycleMPU/hpASICM1 Technology Cycle and MPUTransistors/chip areafter 2013vs.Average2-yearHistoricalMoore’s Law“22nm”/(38nm M1)MPU Model GenerationsSource: ITRS - Executive Summary Fig 8
21 Work in Progress - Do Not Publish 2011 ORTC Table 1 [Unchanged for 2012 Update; tbd 2013 ITRS Renewal]Near-term Years450mm Production Target :‘11 ITRS EUV Intro:DRAM&Flash:MPU:Table ORTC-1 ITRS Technology Trend TargetsYear of Production20112012201320142015201620172018Flash ½ Pitch (nm) (un-contacted Poly)(f)222018171514.213.011.9DRAM ½ Pitch (nm) (contacted)[1,2]363228252320.017.915.9MPU/ASIC Metal 1 (M1) ½ Pitch (nm)[1,2]3827242118.916.915.0MPU High-Performance Printed Gate Length (GLpr) (nm) ††353119.817.715.7MPU High-Performance Physical Gate Length (GLph) (nm)15.314.012.8ASIC/Low Operating Power Printed Gate Length (nm) ††41ASIC/Low Operating Power Physical Gate Length (nm)2619.417.616.014.513.1ASIC/Low Standby Power Physical Gate Length (nm)3017.514.1MPU High-Performance Etch Ratio GLpr/GLph 1.45891.42391.38981.35641.32391.29211.26111.2309MPU Low Operating Power Etch Ratio GLpr/GLph 1.55991.49721.47061.28691.26401.24161.21961.1979?Long-term YearsYear of Production20192020202120222023202420252026Flash ½ Pitch (nm) (un-contacted Poly)(f)10.910.08.98.0DRAM ½ Pitch (nm) (contacted)[1,2]14.212.6184.108.40.206MPU/ASIC Metal 1 (M1) ½ Pitch (nm)[1,2]13.411.910.69.58.47.56.76.0MPU High-Performance Printed Gate Length (GLpr) (nm) ††14.012.5220.127.116.11.96.795.87MPU High-Performance Physical Gate Length (GLph) (nm)18.104.22.168.46.65.9ASIC/Low Operating Power Printed Gate Length (nm) ††6.85.8ASIC/Low Operating Power Physical Gate Length (nm)10.89.87.36.5ASIC/Low Standby Power Physical Gate Length (nm)12.711.410.29.28.2MPU High-Performance Etch Ratio GLpr/GLph 1.20131.17251.14441.11691.09011.06401.03151.0000MPU Low Operating Power Etch Ratio GLpr/GLph 1.17661.15581.13521.11511.09531.07591.0372MPU/hpASIC “Node”(nm): “45” “38” “32” “27” “22.5” “19” “16” “13.4” “11.25” “9.5” “8.0” “6.7” “5.6” “4.73” “4.0” “3.34” “2.81” “2.37” “2.0”2011 ITWG Table Timing:2-year “Node” Cycle /2yrs = /yr2011 ITRS M1 2yr cyc(nm):2011 ITRS M1 3yr cyc (nm):Work in Progress - Do Not Publish
22 Source: 2011 ITRS - Exec. Summary Fig. 3 Technology Cycle Timing Compared to Actual Wafer Production Technology Capacity Distribution* Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 1Q data for 2011. The width of each of the production capacity bars corresponds to the MOS IC production start silicon area for that rangeof the feature size (y-axis). Data are based upon capacity if fully utilized.2.5-Year DRAM Cycle ; 2-year Cycle Flash and MPU201020132-YearDRAMCycle3-YearFeature Size (Half Pitch) (mm)Year>0.7mmmmmmmmmmmmmmmmmmmm<0.06mm19982015= 2003/04 ITRS DRAM Contacted M1 Half-Pitch Actual= 2007/09/11 ITRS DRAM Contacted M1 Half-Pitch Target= 2009/11 ITRS Flash Un-contacted Poly Half Pitch Target= 2009/11 ITRS MPU/hpASIC Contacted M1 Half-Pitch Target4-Year Cycle for Flash after2010 Flash pull-in;MPU 3-yr cycle after 20133-yr cycle for DRAM after pull-in2020Source: ITRS - Exec. Summary Fig. 3*Note: The data for the graphical analysis were supplied by the Semiconductor Industry Association (SIA) from their Semiconductor Industry Capacity Statistics (SICAS). The SICAS data is collected from worldwide semiconductor manufacturers (estimated >90% of Total MOS Capacity) and published by the Semiconductor Industry Association (SIA), as of 1Q11. The detailed data are available to the public online at the SIA website, and data is located at
23 Work in Progress – Do Not Publish! Flash (NAND) Product Size Generations2009 ITRS Renewal:PIDS Flash Size:2007201120162020???4x/4-5yrsWAS'0916G64G256G1TInterim Generations:200920142018202232G128G512G2T5yrs4yrs2011 ITRS Renewal (PIDS 2010 Update Proposal):20102019IS'1120082012201720212026n/a??yrsPoly uncontacted half pitch = 1-year pull-in 2010/23.8nm; then 4-year cycle to 2020; then 3-year cycle; then flat at 8nm/Product memory size: 2 years cycle for introducing 2x product; pull-ins: 1-yr for 32G, 64G, 512G, 1T, 2T; and 2-year for 128G, 256G128Gbit chip will be available in 2012.NAND Cell Array Efficiency unchanged from 56% in ITRS 2010Work in Progress – Do Not Publish!
24 Work in Progress – Do Not Publish! DRAM Product Size Generations2009/10 ITRS Renewal:PIDS DRAM Size:2010201120162017202220234x/6yrs20074G16G64GWAS'09/10Interim Generations:200820132014201920204x/5-6yrs2G8G32G5yrs6yrs2011 ITRS Renewal (PIDS 2010 Update Proposal):20182025n/a4x/7yrsIS'117yrs?DRAM M1 half pitch = 1-year pull-in; then 3-year cycle to 2026DRAM Product Size; Keep ITRS 2009: 2G, 4G, 8G; but 16G delay 1 yr to 2017; add 64G/2025DRAM Cell size factor: 4F2 cell will be available in Delay 2years from ITRS2009/10DRAM Cell Array Efficiency = 59%; versus 56.1% in ITRS 2010Work in Progress – Do Not Publish!
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