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Overall Roadmap Technology Characteristics (ORTC) 2012

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1 Overall Roadmap Technology Characteristics (ORTC) 2012
For ITRS San Francisco Mascone Center Thursday, 7/12/12 1-3:30pm ITRS Public Conference Tracks [Final Rev 6 - includes only Backup I] ITRS Front End of Line Technologies - TechXPOT South, 1-3:30pm ORTC – Alan Allan ITRS Back End of Line Technologies - TechXPOT North, 1-3:30pm ORTC – Bob Doering ITRS CrossCut Technologies - Extreme Electronics Stage, South Hall, 2-3:30pm ORTC – Paolo Gargini

2 ITRS Public Conference Thursday, 07/12/12
ITRS CrossCut Technologies (Extreme Electronics Stage, South Hall, 2:00pm-3:30pm) 2:00-2:05 Greeting from the ITRS IRC Chair IRC Session Chair from Korea 2:05-2:20 Overall Roadmap Technology Characteristics (ORTC) IRC member – Paolo Gargini 2:20-2:35 Factory integration Gopal Rao 2:35-2:50 Environment, safety, and Health Leo Kenny 2:50-3:05 Metrology Alain Diebold 3:05-3:20 Yield enhancement (YE) Lothar Pfitzner 3:20-3:25 Q and A 3:25-3:30 Closing remarks IRC Session Chair ITRS Front End of Line Technologies - TechXPOT South (1:00pm-3:30pm) 1:00-1:05 Greeting from the ITRS IRC Chair IRC Session Chair from Taiwan—Carlos Diaz 1:05-1:20 Overall Roadmap Technology Characteristics (ORTC) IRC member – Alan Allan 1:20-1:35 System drivers Juan-antonio Carballo 1:35-1:50 Design Andrew Kahng 1:50-2:05 Modeling and simulation Juergen Lorenz 2:05-2:20 Process integration, devices, and structures (PIDS) Kwok Ng 2:20-2:35 Lithography Mark Neisser 2:35-2:50 Front end processes (FEP) Mike Walden 2:50-3:05 Emerging research devices (ERD) Victor Zhirnov 3:05-3:20 Emerging research materials (ERM) Michael Garner 3:20-3:25 Q and A 3:25-3:30 Closing remarks IRC Session Chair ITRS Back End of Line Technologies TechXPOT North (1:00pm-3:30pm) 1:00-1:05 Greeting from the ITRS IRC Chair IRC Session Chair from Japan-Hidemi Ishiuchi 1:05-1:20 Overall Roadmap Technology Characteristics (ORTC) IRC member – Bob Doering 1:20-1:40 More than Moore IRC member from Europe 1:40-1:55 Interconnect Paul Zimmerman 1:55-2:10 Assembly and packaging Bill Bottoms 2:10-2:25 Test and Test Equipment Roger Barth 2:25-2:40 Micro-electro-mechanical systems (MEMS) Michael Gaitan 2:40-2:55 RF and analog/mixed-signal technologies (RFAMS) Jack Pekarik 2:55-3:00 Q and A 3:00-3:15 Closing Remarks IRC Session Chair

3 2012 Update ITRS ORTC Technology Trend Summary
Unchanged for 2012: MPU contacted M1 1) 2-year cycle trend through 2013 [27nm (“14nm” node)]; then 3-year trend to 2026 60f2 SRAM 6t cell Design Factor 175f2 Logic Gate 4t Design Factor 2) Unchanged for 2012 Tables: MPU Functions/Chip and Chip Size Models Design TWG Model for Chip Size and Density Model trends – tied to technology cycle timing trends and cell design factors ORTC line item OverHead (OH) area model, includes non-active area Unchanged for 2012 Tables: MPU GLpr, GLph – trends “smoothed” by 2011 PIDS modeling 4) Unchanged for 2012 Tables: Max Chip Frequency trends (reset in 2011 to 3.6Ghz/2010 plus 4% CAGR trend) Unchanged for 2012 Tables: Vdd High Performance, Low operating and standby line items from 2011 PIDS model track “smoothed” gate length changes Note: See PIDS tables for 2012 Update to be released at end of 2012 for impact due to acceleration of MugFET and FDSOI “Equivalent Scaling” timing into 2012

4 2012 Update ITRS ORTC Technology Trend Summary (cont.)
Unchanged for 2012 Tables: DRAM contacted M1: One-year M1 acceleration New for 2012: 4f2 one-year delay to 2014 7) Unchanged for 2012 Tables: Flash Un-contacted Poly: 2+-year pull-in of Poly; however slower 4-year cycle (0.5x per 8yrs) trend to 2020/10nm; then 3-year trend to 2022/8nm; then Flat Poly after 2022/8nm and 3bits/cell extended to 2018; 4bits/cell delay to 2022 Unchanged for 2012 Tables: DRAM Bits/Chip and Chip Size Model: 3-year generation “Moore’s Law” bits/chip doubling cycle target (1-2yr delay for smaller chip sizes <30mm2 – 2x/2.5yrs) Unchanged for 2012 Tables: Flash Bits/Chip and Chip Size Model: 3-year generation “Moore’s Law” bits/chip doubling cycle target (after 1-yr acceleration; then 1-2Tbits; keep chip size <160mm2) 3D on-chip bit layers with relaxed half-pitch tradeoffs are included for maximum bits per chip New 2012 Update Survey Emphasis: layer range from 8/32nm -128/18nm Layers to 16/48nm – 256/24nm Layers (option C in 2011 ORTC Table 2)

5 2012 Update ITRS ORTC Technology Trend Summary (cont.)
10) Unchanged for 2012 Tables: ORTC Table 5 - Litho # of Mask Counts MPU, DRAM, Flash Survey inputs Unchanged for 2012 IC Knowledge (ICK) model contribution extends mask levels range to 2024 Possible 2012 Update consideration: update ICK model to 2011 Mask Counts (only YE impacted) 11) Unchanged for 2012 Update: IRC 450mm Timing Graphic Position: Timing Status to be reviewed with G450C in July, 2012) Consortia work underway IDM and Foundry Pilot lines: ; Production: [corrected early target in 2012 Update] G450C Consortium continues good progress on 450mm program activities to meet the ITRS Timing 1) Consortium operations are using 450mm early test wafer process, metrology and patterning capability to support Supplier development 193 immersion multiple exposure litho tools are under development to support consortium and manufacturers’ schedules for target “1xnm technology” goal 450mm increasing silicon demand is needed from consortium demonstrations to support development 3) Europe Position Unchanged – EEMI450 status was reviewed with IRC in Netherlands Apr’12 4) 300mm wafer generation in parallel line item header with 450mm; Including Technology upgrade assumptions Assuming compatibility of 300mm productivity extensions into the 450mm generation; ITRS-based ICK Strategic Model commercially available and updated to 2011 ITRS, including 300mm and 450mm Range Scenarios for silicon and equipment demand 12) Unchanged for 2012 Update: More than Moore white paper online at MtM Workshop completed in Netherlands, in April and reviewed at Summer ITRS meeting Europe workshop included new iNEMI applications presentation (Grace O’Malley/Europe iNEMI Mgr. – highlights on Automotive; Medical; Energy; Lighting; et al) ITRS MEMS TWG and Chapter cross-roadmap work underway for 2013 iNEMI Roadmap

6 2013 Renewal Preparation ITRS ORTC Technology Trend Summary (cont.)
Technology Pacing Cross-TWG Study Group (CTSG) 2012 work underway to preparation for 2013 ITRS Renewal (kickoff Dec’12), including: IRC Equivalent Scaling Graphic Update Proposals for timing placement of MuGFET, FDSOI, and III/V Ge Timing; now based on one IDM or Foundry company, who may lead technology production ramp Design and FEP Logic Technology Trends Monitor and Update MPU and Leading Edge Logic technology trends, including Ongoing- evaluate alignment of “nodes” with latest M1 industry status Consider High Performance vs. Low Power transistor type needs Consider extending 2yr cycle to 2017/14nm (”7nm” node) Functions/Chip and Chip Size Models tbd; based on final consensus of new proposals On-Chip Frequency Proposals – Align with PIDS modeling and evaluate/update to industry trends PIDS and FEP Memory Survey Proposal Updates Monitor and Update DRAM and Flash technology trends Litho and FEP (and PIDS and Design) Survey for CD Variability and Control Monitor and Update Litho and Etch Gpr/Gph Ratio for CD control trends A&P/Design Power (Thermal) Model Develop proposals for Power Dissipation "hot spot" model rather than chip area basis PIDS/Design Max On-chip Frequency vs Intrinsic Modeling Targeted for 8% (vs. 13%) CAGR (1/CV/I) intrinsic transistor performance (to align with 2011 ITRS 4% Design Frequency trend) Consider Intrinsic Transistor and Ring Oscillator model Changes Including MASTAR static modeling near-term and TCAD dynamic long-term modeling Including “equivalent scaling” tradeoffs (FDSOI, MuGFET, III-V/Ge) with dimensional scaling YE Defect Density Modeling Update ORTC Defect Density model work to latest Litho Mask Count Model – still seeking defect modeling resources support

7 Figure 4 The Concept of Moore’s Law and More
More than Moore: Diversification More Moore: Miniaturization Combining SoC and SiP: Higher Value Systems Baseline CMOS: CPU, Memory, Logic Biochips Sensors Actuators [e.g. MEMS] HV Power Analog/RF Passives 130nm 90nm 65nm 45nm 32nm 22nm 16 nm . V Information Processing Digital content System-on-chip (SoC) Beyond CMOS Interacting with people and environment Non-digital content System-in-package (SiP) Source: ITRS - Exec. Summary Fig. 4

8 Production Ramp-up Model and Technology/Cycle Timing
Figure 2a - (within an established wafer generation*) - *see also Figure 2a for ERD/ERM Research and PIDS Transfer timing; and also - Figure 6 (450mm topic) for Typical Wafer Generation Pilot and Production “Ramp Curves” Production Ramp-up Model and Technology/Cycle Timing 2012 Update Note: Fewer leading IDM Companies Requires Adaption of Definition To allow one IDM Company Or a Foundry Representing Many Fabless Companies To Lead a Technology Production Ramp Timing Months -24 Alpha Tool 12 24 -12 Development Production Beta Pre-Production First Conf. Papers First 1-2 Companies Reaching Combined Production 2 20 200 2K 20K 200K Additional Lead-time: ERD/ERM Research and PIDS Transfer Volume (Wafers/Month) Production Source: ITRS - Exec. Summary Fig. 2a Work in Progress - Do Not Publish

9 Source: 2011 ITRS - Exec. Summary Fig. 2b; plus:
Figure 2b A Typical Technology Production “Ramp” Curve for ERD/ERM Research and PIDS Transfer timing - including an example for III/V Hi-Mobility Channel Technology Timing Scenario - Acceleration to 2015 Scenario for the 2012 Update work Months Alpha Tool Development Production Beta Pre- Volume (Wafers/Month) 2 20 200 2K 20K 200K Research -72 24 -48 -24 -96 Transfer to PIDS/FEP (96-72mo Leadtime) First Tech. Conf. Device Papers Up to ~12yrs Prior to Product 2019 2017 2015 2013 2011 2021 Hi-m Channel Example: 1st 1-2 Co’s Reach Product Circuits Papers Up to ~ 5yrs Hi-m Channel Proposal - for 2013 ITRS work Production Source: ITRS - Exec. Summary Fig. 2b; plus: [http://www.eetimes.com/electronics-news/ /Intel-s-Gargini-pushes-III-V-on-silicon-as-2015-transistor-option ]

10 2012 ITRS Update* 450mm Production Ramp-up Model
[ 2011 ITRS Executive Summary Fig. 6 -  A Typical Wafer Generation Pilot Line and Production “Ramp” Curve] Volume Years Alpha Tool Beta Silicon is supporting development using partially-patterned and processed test wafers  IDM & Foundry  Pilot Lines Manufacturing Demonstrations focus on xnm M1 half-pitch capable tools Development Production Increasing 450mm Silicon Demand From Demonstrations Pre-Production < Consortium  Demonstration 2010 2011 2012 2015 2016 2013 2014 Production *Note:  the IRC recommended updating the ITRS 450mm Timing Graphic for use in the 2011 ITRS Special Topic and 2012 Update Roadmap guidance; based on SEMATECH guidance Source: ITRS - Executive Summary Fig. 6

11 Backup I – Final Rev 5 First (1-10) foils – Public ORTC for Thursday, 7/12 in S.Francisco; Including Backup I (11-24) Foils for the Public Conference (12) ORTC Fig. 3 Memory Trends (13) ORTC Fig. 4 MPU Trends (14) ORTC Fig. 4 MPU Trends with Memory Trends Overlay (15) ORTC Fig. 4 MPU Trends with Memory Trends and Equivalent Scaling Trends Overlay (16) ORTC Fig. 5 Equivalent Scaling Trends Overlay with Leading Company PIDS 2012 ITRS Timing (17) ORTC Fig. 5 Equivalent Scaling Trends Overlay with Fast Follower and 2013 ITRS Timing (18) ORTC Fig. 6 Function Sizes in 2012 ITRS Timing (19) ORTC Fig. 7 Memory Moore’s Law Functions/Chip and Chip Sizes in 2012 ITRS Timing (20) ORTC Fig. 8 MPU Moore’s Law Functions/Chip and Chip Sizes in 2012 ITRS Timing (21) ORTC Table 1 plus 2013 ITRS considerations (22) SICAS Capacity analysis update (23,24) DRAM and Flash Functions/Chip 2009 ITRS vs ITRS (2 foils)

12 [With 2011 Flash 3D Scenario Overlay]
2011 ITRS Figure update; add 3D Flash layer-range emphasis – ORTC Table 1 Graphical Trends – Memory Half Pitch [With 2011 Flash 3D Scenario Overlay] 2012 Update: DRAM: 4f2/’14; Flash: 3D on-chip 2016/16 Layers @ 48nm – option C emphasis 3D - 8 layers 3D layers PIDS 3D Flash : Looser Poly half-pitch /32; Then /28nm /24nm /18nm ~5.5-yr Cycle Long-Term ’19-’26 16nm 3D -16layers/48nm 3D -256layers/24nm 4-yr cycle 5.5-yr cycle Source: ITRS - Executive Summary Fig 3

13 Logic (MPU and high-performance ASIC) Half Pitch and Gate Length
2011 ITRS Figure 4 Unchanged for 2012 – ORTC Table 1 Graphical Trends – Logic (MPU and high-performance ASIC) Half Pitch and Gate Length 2013 CTSG WORK; Update Proposals to be considered Long-Term ’19-’26 16nm Source: ITRS - Executive Summary Fig 4

14 Logic (MPU and high-performance ASIC) Half Pitch and Gate Length
2011 ITRS Figure 4 Unchanged for 2012 – ORTC Table 1 Graphical Trends – Logic (MPU and high-performance ASIC) Half Pitch and Gate Length [ MPU vs. Memory Half-Pitches ] Long-Term ’19-’26 16nm Flash Trends DRAM Trends Source: ITRS - Executive Summary Fig 4

15 M1 pace extension to 2017 ; then 3yrs again
2011 ITRS Figure 4 Unchanged for 2012 – ORTC Table 1 Graphical Trends – Logic (MPU and high-performance ASIC) Half Pitch and Gate Length [ MPU Including PIDS MugFET and FDSOI Acceleration] Long-Term ’19-’26 16nm 2012 ITRS Update Unchanged: “22nm” (ITRS 2011 Planar M1=38nm ; GL=24nm); 3-year Logic M1 Technology Pace after 2013 2-year M1 pace extension to ; then 3yrs again [ also including Memory Half-Pitches Cartoon trends For comparison ] Flash Trends DRAM Trends 2013 ITRS Work Consider: “7nm” pull-in to 2017 (from ITRS 2011 Planar M1=14nm/’19)?; III/V Ge pull-in to 2015?; ITRS GLph = 11.7nm unchanged?; Logic and Flash (3yr cycle) both drive Lithography after 2017; Logic M1 after 2022? MuG-FET FDSOI Hi-u,(tbd) Source: ITRS - Executive Summary Fig 4

16 Sub-Team Transistor Modeling Work Underway for
UPDATED 06/24/12 FOR IRC and 2012 CTSG WORK And 2013 ITRS Preparation 2011 ITRS Figure 5 “Equivalent Scaling” Roadmap for Logic (MPU and high performance ASIC) Figure 5 ORTC Table 1 Graphical Trends (including overlay of 2009 industry logic “nodes” and ITRS trends for comparison); also including proposals for MugFET and FDSOI (2012) ITRS acceleration [ PIDS/FEP/Design HP/LOP/LSTP Sub-Team Transistor Modeling Work Underway for 2013 ITRS ] Metal High k Gate-stack material 2009 2012 2015 2018 2021 Bulk FDSOI Multi-gate (on bulk or SOI) Structure (electrostatic control) Channel material 2nd generation Si + Stress S D High-µ InGaAs; Ge PDSOI nth generation Possible Delay Possible Pull -in 16 68nm 45nm 32nm 22nm 16nm 2011 ITRS DRAM M1 : 2011 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm nm nm MPU/hpASIC “Node”: “45nm” “32nm” “22/20nm” “16/14nm” “11/10nm” “8/7nm” 2011 ITRS hi-perf GLph : nm 29nm 29nm 27nm 24nm 22nm 20nm nm nm 2011 ITRS hi-perf GLpr : nm 47nm 47nm 41nm 35nm 31nm 28nm nm nm 11nm 2011 ITRS Flash Poly : 54nm 2011 ITWG Table Timing: PIDS Acceleration - for 2012 ITRS Update 22-24 8nm 2024 15nm 450mm 1st Production 2012 Update Note: Leadership company First Manu- facturing could set more Aggressive first production target, since “fast followers” may trail 1-3 years Source: ITRS - Executive Summary Fig 5

17 Source: 2011 ITRS - Executive Summary Fig 5
2011 ITRS Figure 5 “Equivalent Scaling” Roadmap for Logic (MPU and high performance ASIC) Figure 5 ORTC Table 1 Graphical Trends (including overlay of 2009 industry logic “nodes” and ITRS trends for comparison); also including proposals for MugFET and FDSOI (2012) and III/V Ge (2013) ITRS acceleration Metal High k Gate-stack material 2009 2012 2015 2018 2021 Bulk FDSOI Multi-gate (on bulk or SOI) Structure (electrostatic control) Channel material 2nd generation Si + Stress S D High-µ InGaAs; Ge PDSOI nth generation Possible Delay Possible Pull -in 17 68nm 45nm 32nm 22nm 16nm 2011 ITRS DRAM M1 : 2011 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm nm nm MPU/hpASIC “Node”: “45nm” “32nm” “22/20nm” “16nm/14nm” “11/10nm” “8/7nm” 2011 ITRS hi-perf GLph : nm 29nm 29nm 27nm 24nm 22nm 20nm nm nm 2011 ITRS hi-perf GLpr : nm 47nm 47nm 41nm 35nm 31nm 28nm nm nm 11nm 2011 ITRS Flash Poly : 54nm 2011 ITWG Table Timing: PIDS Acceleration - for 2012 ITRS Update 22-24 8nm 2024 15nm Proposal - for 2013 ITRS prep. MPU = DRAM 2015 on M1 2-yr Cycle? MPU < 2017 on FDSOI MugFET pull-in to “14nm”/2014? “…IBM will move to finFETs based on silicon-on-insulator wafers at the 14 nm node….” “…You don’t need well contacts. And anyone who does a cost analysis will conclude that the cost of isolation in bulk is comparable to the cost of the SOI wafer…” “…IBM has developed an embedded DRAM technology on its current SOI platform, he said carrying eDRAM forward to vertical transistors will be relatively straightforward…” “…The Fishkill Alliance of companies, including Samsung, GlobalFoundries, Toshiba, and others, will pursue bulk finFETs at the 14nm node…” MPU/hpASIC “Node”(nm): “45” “38” “32” “27” “22.5” “19” “16” “13.4” “11.25” “9.5” “8.0” “6.7” “5.6” “4.73” “4.0” “3.34” “2.81” “2.37” “2.0” 2011 ITWG Table Timing: 2-year “Node” Cycle /2yrs = /yr 2011 ITRS M1 2yr cyc(nm): 2011 ITRS M1 3yr cyc (nm): Multiple companies with Bulk MugFET pull-in to “14nm”/2014? 2012 Update Note: Leadership company First Manu- facturing could set more Aggressive first production target, since “fast followers” may trail 1-3 years ? UPDATED 06/24/12 FOR IRC and 2012 CTSG WORK And 2013 ITRS Preparation

18 Product Function Size Trends Unchanged; except 4f2 moved to 2014
2011 ORTC Figure 6 Product Function Size Trends Unchanged; except 4f2 moved to 2014 PIDS NAND Flash Multi-Layer 3D Model vs. “Slower” Poly half-pitch Dimensional Reduction Rate affects 3D Bit size & density (not graphed) Long-Term ’19-’26 2011 ITRS: Updated 06/24/12 FOR 2012 CTSG WORK [transistor + capacitor] Source: ITRS - Executive Summary Fig 6 MPU/ASIC Alignment Design TWG Actual SRAM [60f2] & Logic Gate [175f2] DRAM 4f2 Added WAS:Begin in 2011 IS: Delayed To 2013 ‘14 Flash [4f2] 1) 2-yr Cycle Extended to 2010; 2) 3 bits/cell added [and extended to 2026 in the 2011 ITRS]; 3) 4 bits/cell moved from 2012 [to 2021 in the 2011 ITRS] 3D - 8 layers 3D layers 3D -16layers/48nm? 3D -256layers/24nm? 4-yr cycle? 5.5-yr cycle Flash Impact of: Vs:

19 Figure ITRS Product Technology Trends: Memory Product Functions/Chip and Industry Average “Moore’s Law” and Chip Size Trends [unchanged for the 2012 Update] Long-Term ’19-’26 2011 ITRS: 2011 4Tbits Possible with PIDS NAND Flash Multi-Layer 3D Model Scenario Option DRAM 4f2 Added WAS:Begin in 2013 IS: Delayed To 2013 ‘14 3D layers/ ‘25 2025/32nm/3bits/cell 4Tbits =128x33Gbits 2025/18nm/3bits/cell 13Tbits =128x99Gbits Source: ITRS - Executive Summary Fig 7

20 [unchanged for 2012 Update]
Figure ITRS Product Technology Trends: MPU Product Functions/Chip and Industry Average “Moore’s Law” and Chip Size Trends [unchanged for 2012 Update] <260mm2 <140mm2 MPU = 2x/3yrs = 2x/2yrs Average "Moore's Law" = 2x/2yrs Long-Term ’19-’26 2011 ITRS: 2011 ITRS: Unchanged, but Extend ed Transistors/chip & Chip Size Models to 2026 On 3-year Cycle MPU/hpASIC M1 Technology Cycle and MPU Transistors/chip are after 2013 vs. Average 2-year Historical Moore’s Law “22nm”/(38nm M1) MPU Model Generations Source: ITRS - Executive Summary Fig 8

21 Work in Progress - Do Not Publish
2011 ORTC Table 1 [Unchanged for 2012 Update; tbd 2013 ITRS Renewal] Near-term Years 450mm Production Target : ‘11 ITRS EUV Intro: DRAM&Flash: MPU: Table ORTC-1 ITRS Technology Trend Targets Year of Production 2011 2012 2013 2014 2015 2016 2017 2018 Flash ½ Pitch (nm) (un-contacted Poly)(f)[2] 22 20 18 17 15 14.2 13.0 11.9 DRAM ½ Pitch (nm) (contacted)[1,2] 36 32 28 25 23 20.0 17.9 15.9 MPU/ASIC Metal 1 (M1) ½ Pitch (nm)[1,2] 38 27 24 21 18.9 16.9 15.0 MPU High-Performance Printed Gate Length (GLpr) (nm) ††[1] 35 31 19.8 17.7 15.7 MPU High-Performance Physical Gate Length (GLph) (nm)[1] 15.3 14.0 12.8 ASIC/Low Operating Power Printed Gate Length (nm) ††[1] 41 ASIC/Low Operating Power Physical Gate Length (nm)[1] 26 19.4 17.6 16.0 14.5 13.1 ASIC/Low Standby Power Physical Gate Length (nm)[1] 30 17.5 14.1 MPU High-Performance Etch Ratio GLpr/GLph [1] 1.4589 1.4239 1.3898 1.3564 1.3239 1.2921 1.2611 1.2309 MPU Low Operating Power Etch Ratio GLpr/GLph [1] 1.5599 1.4972 1.4706 1.2869 1.2640 1.2416 1.2196 1.1979 ? Long-term Years Year of Production 2019 2020 2021 2022 2023 2024 2025 2026 Flash ½ Pitch (nm) (un-contacted Poly)(f)[2] 10.9 10.0 8.9 8.0 DRAM ½ Pitch (nm) (contacted)[1,2] 14.2 12.6 11.3 7.1 6.3 MPU/ASIC Metal 1 (M1) ½ Pitch (nm)[1,2] 13.4 11.9 10.6 9.5 8.4 7.5 6.7 6.0 MPU High-Performance Printed Gate Length (GLpr) (nm) ††[1] 14.0 12.5 11.1 9.9 8.8 7.9 6.79 5.87 MPU High-Performance Physical Gate Length (GLph) (nm)[1] 11.7 9.7 8.1 7.4 6.6 5.9 ASIC/Low Operating Power Printed Gate Length (nm) ††[1] 6.8 5.8 ASIC/Low Operating Power Physical Gate Length (nm)[1] 10.8 9.8 7.3 6.5 ASIC/Low Standby Power Physical Gate Length (nm)[1] 12.7 11.4 10.2 9.2 8.2 MPU High-Performance Etch Ratio GLpr/GLph [1] 1.2013 1.1725 1.1444 1.1169 1.0901 1.0640 1.0315 1.0000 MPU Low Operating Power Etch Ratio GLpr/GLph [1] 1.1766 1.1558 1.1352 1.1151 1.0953 1.0759 1.0372 MPU/hpASIC “Node”(nm): “45” “38” “32” “27” “22.5” “19” “16” “13.4” “11.25” “9.5” “8.0” “6.7” “5.6” “4.73” “4.0” “3.34” “2.81” “2.37” “2.0” 2011 ITWG Table Timing: 2-year “Node” Cycle /2yrs = /yr 2011 ITRS M1 2yr cyc(nm): 2011 ITRS M1 3yr cyc (nm): Work in Progress - Do Not Publish

22 Source: 2011 ITRS - Exec. Summary Fig. 3
Technology Cycle Timing Compared to Actual Wafer Production Technology Capacity Distribution * Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 1Q data for 2011.  The width of each of the production capacity bars corresponds to the MOS IC production start silicon area for that range of the feature size (y-axis). Data are based upon capacity if fully utilized. 2.5-Year DRAM Cycle ; 2-year Cycle Flash and MPU 2010 2013 2-Year DRAM Cycle 3-Year Feature Size (Half Pitch) (mm) Year >0.7mm mm mm mm mm mm mm mm mm mm <0.06mm 1998 2015 = 2003/04 ITRS DRAM Contacted M1 Half-Pitch Actual = 2007/09/11 ITRS DRAM Contacted M1 Half-Pitch Target = 2009/11 ITRS Flash Un-contacted Poly Half Pitch Target = 2009/11 ITRS MPU/hpASIC Contacted M1 Half-Pitch Target 4-Year Cycle for Flash after 2010 Flash pull-in; MPU 3-yr cycle after 2013 3-yr cycle for DRAM after pull-in 2020 Source: ITRS - Exec. Summary Fig. 3 *Note: The data for the graphical analysis were supplied by the Semiconductor Industry Association (SIA) from their Semiconductor Industry Capacity Statistics (SICAS). The SICAS data is collected from worldwide semiconductor manufacturers (estimated >90% of Total MOS Capacity) and published by the Semiconductor Industry Association (SIA), as of 1Q11. The detailed data are available to the public online at the SIA website, and data is located at

23 Work in Progress – Do Not Publish!
Flash (NAND) Product Size Generations 2009 ITRS Renewal: PIDS Flash Size: 2007 2011 2016 2020 ??? 4x/4-5yrs WAS'09 16G 64G 256G 1T Interim Generations: 2009 2014 2018 2022 32G 128G 512G 2T 5yrs 4yrs 2011 ITRS Renewal (PIDS 2010 Update Proposal): 2010 2019 IS'11 2008 2012 2017 2021 2026 n/a ??yrs Poly uncontacted half pitch = 1-year pull-in 2010/23.8nm; then 4-year cycle to 2020; then 3-year cycle; then flat at 8nm/ Product memory size: 2 years cycle for introducing 2x product; pull-ins: 1-yr for 32G, 64G, 512G, 1T, 2T; and 2-year for 128G, 256G 128Gbit chip will be available in 2012. NAND Cell Array Efficiency unchanged from 56% in ITRS 2010 Work in Progress – Do Not Publish!

24 Work in Progress – Do Not Publish!
DRAM Product Size Generations 2009/10 ITRS Renewal: PIDS DRAM Size: 2010 2011 2016 2017 2022 2023 4x/6yrs 2007 4G 16G 64G WAS'09/10 Interim Generations: 2008 2013 2014 2019 2020 4x/5-6yrs 2G 8G 32G 5yrs 6yrs 2011 ITRS Renewal (PIDS 2010 Update Proposal): 2018 2025 n/a 4x/7yrs IS'11 7yrs? DRAM M1 half pitch = 1-year pull-in; then 3-year cycle to 2026 DRAM Product Size; Keep ITRS 2009: 2G, 4G, 8G; but 16G delay 1 yr to 2017; add 64G/2025 DRAM Cell size factor: 4F2 cell will be available in Delay 2years from ITRS2009/10 DRAM Cell Array Efficiency = 59%; versus 56.1% in ITRS 2010 Work in Progress – Do Not Publish!


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