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Nov 29, 2001 ITRS Conference Assembly and Packaging Joe Adam TWIG Co-chair.

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Presentation on theme: "Nov 29, 2001 ITRS Conference Assembly and Packaging Joe Adam TWIG Co-chair."— Presentation transcript:

1 Nov 29, 2001 ITRS Conference Assembly and Packaging Joe Adam TWIG Co-chair

2 Nov 29, 2001 ITRS Conference Key Contributors Xavier Baraton Mark Bird - Amkor Bill Bottoms - 3MTS Ken Brown - Intel Chi Shih Chang - K&S Bill Chen - ASE Peter Elenius - K&S Hisao Kasuga - NEC Ed Fulcher - LSI Logic Ron Gedney - NEMI Seiji Hamano - Fujitsu Mahadevan Iyer - IME Bernd Roemer - IFX John Stankus - Nortel Henry Utsunomiya- JISSO Jurgen Wolf - IZM

3 Nov 29, 2001 ITRS Conference Packaging and Assembly Chapter Updates New text sections added to address emerging technology requirements –Packaging Design –Packaging Materials –Packaging Reliability –MEMS Packaging –Optoelectronics –Embedded Passives Updates on requirements for –Mixed signal and RF packaging –Multi-chip packaging –Flip chip interconnect –Thermal management –BGA and CSP Packaging

4 Nov 29, 2001 ITRS Conference Compatibility Between Roadmaps Focus participation of JEITA (Jisso) chair to co-ordinate Roadmap inputs between regions and industry groups Direct co-ordination with IPC and NEMI on packaging Roadmaps Provide a general bridge through packaging to the electronic industry Roadmap efforts

5 Nov 29, 2001 ITRS Conference Market Sectors We have used the NEMI market sector definitions from 2000 but expect these will be redefined by NEMI in 2002 –Low cost - <$300 consumer products –Hand held - <$1000 battery powered –Cost performance <$3000 notebooks, desktop –High performance >$3000 workstations, servers, network switches –Harsh - Under the hood, and other hostile environments –Memory - Flash, DRAM, SRAM

6 Nov 29, 2001 ITRS Conference Difficult Challenges Near Term Tools and methodologies to address chip and package co-design –Mixed signal co-design and simulation (SI, Power, EMI) –For transient and localized hot spots - simulation of thermal mechanical stresses, thermal performance and current density in solder bumps Improved Organic substrates –Increased wireability and dimensional control at low cost –Higher temperature stability, lower moisture absorption, higher frequency capability Improved (or elimination of) underfills for flip chip –Improved underfill integration, adhesion, faster cure, higher temperature Impact of Cu/low k on Packaging –Direct wire bond and UBM/bump to Cu to reduce cost –Lower strength in low k which creates a weaker mechanical structure Pb free and green materials at low cost –Technical approaches are well defined but cost is not in line with needs

7 Nov 29, 2001 ITRS Conference Difficult Challenges Long Term Package cost may greatly exceed die cost –Present R&D investments do not address this effectively System level view to integrate chip, package, and system design –Design will be distributed across industry specialist Small high frequency, high power density, high I/O density die Increasing gap between device, package and board wiring density –Cost of high density package substrates will dominate product cost

8 Nov 29, 2001 ITRS Conference Changes to Requirements Tables Cost per pin numbers have adjusted down across all segments –No Known solutions for many out year targets –Cost targets still put the cost of packaging well above cost of die Pin counts have been adjusted down –Pin counts still drive wiring density in packages very aggressively –Signal and reference ratios added to help clarify test and design requirements Power will continue to increase in the high end and related frequency for I/O has been increased to include new communications requirements

9 Nov 29, 2001 ITRS Conference Crosscut issues Modeling of thermal and mechanical issues at package and device level which impact interconnect, test, design, modeling groups –Stress transfer from package to device level –Handling of lower strength low k dielectric structures –Materials properties are not available for many applications –Device performance skew due to temperature differences that are driven by package design and system applications Power and pin count trends for design and test –Probe, contactors, handling to cover pin count, pitch, power and frequency –Pin count which increases with flat die size which drives rapid increase in I/O density Rapid increase in frequency for emerging high speed serial I/O –Impacts design, test

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