1. Tehran University Faculty of Engineering VLSI Course Class Presentation Fall 1383 Professor: DR Fakhraei Presenter: Nasim Hajary

2. Low-power Circuits and Technology for Wireless Digital Systems Authors: S. V. Kosonocky, A. J. Bhavnagarwala, K. Chin,G. D. Gristede A.-M. Haen, W. Hwang, M. B. Ketchen, S. Kim D. R. Knebel, K. W. Warren, V. Zyuban

3. Outlines: Introduction Deep submicron CMOS technology limitations Low power circuit techniques Multi threshold design methodology Power Gating techniques Conclusion

4. Introduction: The importance for wristwatch computer such as the IBM WatchPad* or WorkPad*, or a cellular telephone is speed and low-power consumption. Also CMOS technology scales to deep submicron dimensions, power plays the most important role.

5. Technology: power consumption due to component leakage begins to surpass dynamic power

6. Low-power circuit styles: Optimizing the circuit style:  Static CMOS has the lowest sensitivity to process variations The power dissipation in CMOS circuits consists of several main components, as shown in Equation below: P(total) = P(sw) + P(sc) + P(static) + P(leak)

7. Usage of multi threshold devices: These logic circuits incorporate one set of low-Vt devices and another set of high-Vt devices. The key techniques are to use the low-Vt device to gain performance, high-Vt devices to cut off the leakage paths.

8. Usage of multi threshold devices:

9. Power gating: Header or footer with high Vt can be used to decouple the logic from supply or ground during long idle period or sleep state. To compensate the reduction in logic performance these switches are bigger in size.

10. Power gating:

11. Conclusion: Advanced technology imposes new limitations on the circuit designer Leakage power is a major constraint for low-power battery-operated applications A combination of system architecture, circuit style, and technology options can allow long battery life while providing high performance on demand for new applications. Low Vt devices allow high performance but also high standby leakage power. High Vt devices decrease leakage power and cause more delay.

12. References: 1. E. J. Nowak, “Maintaining the Benefits of CMOS Scaling When Scaling Bogs Down,” IBM J. Res. & Dev. 46, No. 2/3, 169 –180 (March/May 2002). 2. J. Burr and A. Peterson, “Energy Considerations in Multichip-Module-Based Multiprocessors,” Proceedings of the International Conference on Computer Design, September 1999, pp. 593– 600. 3. K. Bernstein, K. Carrig, C. Durham, and P. Hansen, High Speed CMOS Design Styles, Kluwer Academic Publications, New York, 1998. 4. A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, Boston, 1995.