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1 Cleared for Open Publication July 30, 2004 04-S-2144 P148/MAPLD 2004 Rea MAPLD 148:"Is Scaling the Correct Approach for Radiation Hardened Conversions.

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Presentation on theme: "1 Cleared for Open Publication July 30, 2004 04-S-2144 P148/MAPLD 2004 Rea MAPLD 148:"Is Scaling the Correct Approach for Radiation Hardened Conversions."— Presentation transcript:

1 1 Cleared for Open Publication July 30, S-2144 P148/MAPLD 2004 Rea MAPLD 148:"Is Scaling the Correct Approach for Radiation Hardened Conversions of Deep Submicron Microprocessors?" D. Rea, D. Bayles, A. Kazemzadeh, F. Thoma, and N. Haddad

2 2 Cleared for Open Publication July 30, S-2144 P148/MAPLD 2004 Rea Introduction Opportunity: Provide faster and lower power devices for satellite applications through the use of advanced technologies –Migrate existing designs to new technologies –Develop new designs in new technologies Migration Challenge: Affordably maximize benefits of new technologies Situation: Migrate a 0.25u CMOS version of the RAD750 TM to both a 0.18u CMOS process and a 0.15u CMOS process and increase performance by ~33% at 0.18u and ~50% at 0.15u –All technologies are bulk CMOS –Transistor behavior and back end metallurgy are very compatible Increasing demands for highly reliable, radiation hardened processing power on satellites continue to push the capabilities of technology.

3 3 Cleared for Open Publication July 30, S-2144 P148/MAPLD 2004 Rea Challenge: Increase microprocessor performance at each technology node without a degradation in radiation performance while maintaining affordability. Title III Radiation Hardened Microprocessor for Space Program Goals Prototypes 4/06 Flight parts 7/06

4 4 Cleared for Open Publication July 30, S-2144 P148/MAPLD 2004 Rea Custom Blocks -Harden RAM cells, sense amps, and decoders -Harden latches and clocks -Harden PLL and add temperature compensation -Replace dynamic logic with static equivalents -Design circuits to minimize injected pulses -Replace low Vt devices Standard Cells (RLMs) (Control Logic) -Harden latches and clock splitters -Design circuits to minimize injected pulses -Replace low Vt devices l Complex Cells (OTS) (Data Flow ) -Harden latches and clock splitters -Replace dynamic logic with static equivalents -Design circuits to minimize injected pulses -Replace low Vt devices Circuit Families in the RAD750™ A variety of circuit families were utilized in the RAD750 to provide density and performance. Modifications were made to all circuit types to harden the design.

5 5 Cleared for Open Publication July 30, S-2144 P148/MAPLD 2004 Rea Scaling Options The objective is to pick the highest performance at lowest cost migration option. Gate shrink only (one dimension, 1D) –Pro: drive current increases from larger W/L –Pro: simple to implement –Pro: minimal impact to floorplan –Con: no decrease in die size or wiring parasitics –Con: uneven performance improvement Two dimensional shrink (2D) –Pro: die size and parasitics decrease –Con: uneven performance improvement –Con: greater perturbation to routing Hybrid approach (combination of 1D, 2D shrinks and circuit optimization) –Pro: achieve balanced improvement –Con: increase in effort to implement (circuit level and full chip)

6 6 Cleared for Open Publication July 30, S-2144 P148/MAPLD 2004 Rea Scaling Options - Standard Cell Study (RLMs) Largest average improvement observed with 1 dimensional scaling plus compaction. However, minimal cell size reduction yields little parasitic reduction, so advantage seen with no load is lost when loads are taken into consideration. 1D - 1 dimension scaling, 2D - 2 dimension scaling, C - scaling with compaction

7 7 Cleared for Open Publication July 30, S-2144 P148/MAPLD 2004 Rea Largest average improvement observed with 2 dimensional scaling plus compaction. However, performance improvement is not uniform across all cells. Scaling Options - Standard Cell Study (RLMs) 1D - 1 dimension scaling, 2D - 2 dimension scaling, C - scaling with compaction

8 8 Cleared for Open Publication July 30, S-2144 P148/MAPLD 2004 Rea As expected, reduced power supply voltage accounts for majority of power reduction. Overall chip power will increase when frequency of operation increases. Scaling Options - Standard Cell Study (RLMs) 1D - 1 dimension scaling, 2D - 2 dimension scaling, C - scaling with compaction

9 9 Cleared for Open Publication July 30, S-2144 P148/MAPLD 2004 Rea Scaling Options - Complex Cells (Data Flow) Study Using two dimensional scaling, the non-uniformity in performance improvement shows that the average is misleading. Should the “slower” cells end up in the critical path, overall speed could go down. Use “as is” until first full chip timing run Optimize or synthesize as necessary to improve performance

10 10 Cleared for Open Publication July 30, S-2144 P148/MAPLD 2004 Rea Custom macros are the heart of the processor, representing over 2/3 the total transistor count and driving the critical performance paths. Scaling Options - Custom Macros

11 11 Cleared for Open Publication July 30, S-2144 P148/MAPLD 2004 Rea The MMU/TAG/CACHE paths on both the instruction and data sides comprise the processor critical path. Scaling Options - Custom Macros

12 12 Cleared for Open Publication July 30, S-2144 P148/MAPLD 2004 Rea As with the data flow complex cell macros (see p. 9), scaling of the custom macros produced uneven results. Scaling Options - Custom Macro Study 1D scaling was chosen for the custom macros for the following reasons Critical node spacing in the memory arrays had to be maintained Because of the amount of custom layout in these macros, simple 2D scaling resulted in a very large number of DRC errors that would have required considerable manual intervention to correct 1D Scaling Results

13 13 Cleared for Open Publication July 30, S-2144 P148/MAPLD 2004 Rea Custom Blocks -1D Scale as baseline (minimize cost) -Optimize circuit design (new topologies, layout structure) as necessary Standard Cells -Resize transistors -Automatically generate layouts (~2D scaling) -Resynthesize at chip level l Complex Cells -2D scale where appropriate -Optimize when possible -Synthesize from standard cells where economically advantageous and performance isn’t required. Scaling Solution for the RAD750™ Bottom line - scaling by itself is not sufficient to meet performance goals. Scaling combined with other techniques supports the performance goals at a reasonable cost.

14 14 Cleared for Open Publication July 30, S-2144 P148/MAPLD 2004 Rea Predicted Performance of RAD750™ By combining scaling with other design techniques, program goals can be met at an affordable price.

15 15 Cleared for Open Publication July 30, S-2144 P148/MAPLD 2004 Rea Summary Simple scaling is not sufficient to meet performance objectives at advanced technology nodes –improvements are not uniform –improvements from scaling don’t meet objectives even if average was uniform To maintain affordability, a hybrid approach consisting of several scaling techniques and circuit optimization was selected to maximize the advantages of the advanced technologies Automation is used where possible to support changes in technology groundrules and support conversion to future technologies –Additional automation in the custom macro area required to resolve issues with simple scaling Program goals can be met with the hybrid approach


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