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Leakage Energy Management in Cache Hierarchies L. Li, I. Kadayif, Y-F. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, and A. Sivasubramaniam Penn State.

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Presentation on theme: "Leakage Energy Management in Cache Hierarchies L. Li, I. Kadayif, Y-F. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, and A. Sivasubramaniam Penn State."— Presentation transcript:

1 Leakage Energy Management in Cache Hierarchies L. Li, I. Kadayif, Y-F. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, and A. Sivasubramaniam Penn State University PACT-2002 Charlottesville, Virginia September 22-25, 2002

2 Outline Motivation Related works Circuit support for leakage control Leakage optimization strategies Integration with other strategies Conclusion Future works

3 Motivation Leakage energy is projected to become the dominant portion of the chip power budget for 0.10 micron technology and below. A. Chandrakasan et al., Design of High-Performance Microprocessor Circuits. Leakage energy is of particular concern in dense cache memories that form a major portion of the transistor budget.

4 Related Works M. D. Powell et al. An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches.(HPCA-7) S. Kaxiras et al. Cache decay: exploiting generational behavior to reduce cache leakage power. (ISCA-28) H. Zhou et al. Adaptive mode control: A static-power-efficient cache design. (PACT’01) K. Flautner et al. Drowsy caches: Simple techniques for reducing leakage power. (ISCA-29) Y-F. Tsai et al. A sizing model for SRAM data preserving sleep transistors. (ASIC’02)

5 Circuit Support for Leakage Control State-destroying mechanism. ( Gated-V dd ) Introduce a power-switch between the ground and the circuit to reduce leakage. Sizing to maximize the static power saving but lose data in cells. State-preserving mechanism. ( Modified Gated-V dd ) Appropriately sizing NMOS power-switch to provide the required minimum supply voltage to maintain the state of a static memory cell.

6 State-preserving Leakage Control

7 Leakage Optimization Strategies Employ state-destroying or state-preserving mechanisms in cache. For single block, state-destroying mechanism saves more leakage energy than state-preserving mechanism. For whole cache hierarchies, state-destroying mechanism pays a higher miss penalty. Exploit data duplication in the cache hierarchy. Data duplication: data in L2 subblocks also exist in L1 blocks. Implement five leakage reduction strategies.

8 Leakage Optimization Strategies (II) StrategyWhen is L2 subblock turned off? Mechanism in L2 When is L2 subblock reactivated? Conservativewhen L1 block becomes dirty state-destroyingwhen accessed Speculative-Iwhen L2 subblock is moved to L1 state-preservingwhen accessed Speculative-IIwhen L2 subblock is moved to L1 state-destroyingwhen accessed Speculative-IIIwhen L2 subblock is moved to L1 state-preservingwhen L1 block is evicted Speculative-IVwhen L2 subblock is moved to L1 state-destroyingwhen L1 block is evicted

9 Conservative L1L2 Active Destroying Write load Only deactivate dead L2 subblocks. Before written in L1, both two copies of data are in active mode.

10 Speculative-I L1L2 Active load Preserving re-access Active evict Put L2 subblock in state-preserving mode when data is brought from L2 to L1. Not lose data in L2 and need time to reactivate L2 subblock when re-access.

11 Speculative-II L1L2 Active load re-access evict DestroyingActive load Put L2 subblock in state-destroying mode when data is brought from L2 to L1. Lose data in L2 and need longer time to load data from main memory when re-access.

12 Speculative-III L1L2 Active load PreservingActive evict Similar to Speculative-I except that L2 subblock reactivated when L1 block is replaced. Hide reactivation time.

13 Speculative-IV L1L2 Active load evict and Write back DestroyingActive Similar to Speculative-II except that L2 subblock is written back when L1 block is replaced.

14 Experimental Configuration Technology0.07 micron Supply Voltage1.0V Virtual Supply Settling Time50 cycles Dynamic Energy per L1 Access0.565nJ Dynamic Energy per L2 Access5.83nJ Leakage Energy per L1 Block per Active Cycle 0.551pJ Leakage Energy per L2 Subblock per Standby Cycle (state-preserving) 0.055pJ Leakage Energy per L2 Subblock per Standby Cycle (state-destroying) 0pJ Control Energy0.055nJ

15 Result of Energy Saving Conservative Speculative-I Speculative-II Speculative-III Speculative-IV

16 Result of Energy-delay Saving Conservative Speculative-I Speculative-II Speculative-III Speculative-IV

17 Average Saving of Five Strategies

18 Integration With Other Strategies Cache decay Exploiting generational behavior and use state-destroying mechanism to reduce cache leakage energy. Implement four strategies L1L2 Decay-Icache decaystate-destroyingcache decaystate-destroying Decay-IIcache decaystate-destroyingcache decaystate-preserving Speculative -Decay-I cache decaystate-destroyingspeculative-Istate-preserving Speculative -Decay-II cache decaystate-destroyingcache decay + speculative-I state-preserving

19 Result of Energy Saving Decay-I Decay-II Speculative-Decay-I Speculative-Decay-II

20 Result of Energy-delay Saving Decay-I Decay-II Speculative-Decay-I Speculative-Decay-II

21 Average Savings of Strategies

22 Conclusion Duplication of data at different levels of memory hierarchy is costly from the leakage energy perspective. Applying state-preserving leakage control strategy to L2 cache can reduce energy consumption significantly. Our strategies can be combined with other techniques to provide additional energy gains.

23 Future Works More powerful combined optimization strategies. Combining state-preserving and state- destroying strategies. Software-based leakage optimization. Integrating hardware-based and software-based strategies.

24 Thanks !


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