1. Digital Logic Synthesis for Memristors1

2. Memristor One type of new emerging nano-devices
Memory-Resistor postulated by Leon Chua in 1971
First physical implementation found by HP in 2008 2

3. Memristor 3

4. Memristor in Digital Logic
Threshold device
Crossing threshold switches the resistance/conductance of the memristor
Information is stored in the resistive state
Non-volatile resistance
No refresh needed
Can switch in nano-seconds with pico-joule energy (cite HP paper)
Has the potential for high density, low power logic and memory circuits 4

5. Published synthesis methods
Julien Borghetti, Gregory S. Snider, Philip J. Kuekes, J. Joshua Yang, Duncan R. Stewart, and R. Stanley Williams. /‘memristive/’ switches enable /‘stateful/’ logic operations via material implication. Nature, 464:873 –876,
A. Chattopadhyay and Z. Rakosi. Combinational logic synthesis for material implication. In VLSI and System-on-Chip (VLSISoC), 2011 IEEE/IFIP 19th International Conference on, pages 200 –203, Oct Different assumptions
E. Lehtonen and M. Laiho. Stateful implication logic with memristors. In Nanoscale Architectures, NANOARCH ‘09. IEEE/ACM International Symposium on, pages 33 –36, July 2009.
E. Lehtonen, J.H. Poikonen, and M. Laiho. Two memristors suffice to compute all boolean functions. Electronics Letters, 46(3):239 –240,
J.H. Poikonen, E. Lehtonen, and M. Laiho. On synthesis of boolean expressions for memristive devices using sequential implication logic. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 31(7):1129 –1134, July 2012.
D.B. Strukov, A. Mishchenko, and R. Brayton, Maximum Throughput Logic Synthesis for Stateful Logic: A Case Study, preprint. Different assumptions

6. Material Implication Conditional logic with multiple interpretations
If p then q
q follows p
...
Paradox of entailment
An argument (p->q) is false, iff the premise (p) is true and the conclusion (q) is false p
pq = p  q
p  q q 6

7. IMPLY Logic
Two memristors can perform material implication with one pulse – IMPLY
Consider memristors as a switch with two states – Ron, Roff
Voltage drop over P affects voltage drop over Q
Result will be stored in Q
Q is input and output memristor 7

8. IMPLY Logic - Notes Explains the conditions for Q changing its state
Q is pre-set to “0” (low conductance / high resistance)
Voltage level V_Rg determines voltage drop over Q
Only if P = “0” V_Rg remains low and allows Q to change 8

9. Material Implication with Memristors9

10. Material Implication - Notes
5 pulses, 4 input patterns
First two pulses to show initial input values of P and Q
Third pulse performs operation (two pulses applied simultaneously to P and Q)
Fourth and fifth pulses to read resulting values of P and Q
Note different pulse amplitude during pulse three (V_set, V_cond) 10

11. Why are we interested in that?
CMOS technology scaling is approaching limits
Main limitation in modern CPUs is heat
2-terminal device of 10nm size
Allow much higher/denser device integration
Switching between states can be done with pico Joule 11

12. Building NAND from IMPLY
IMPLY & FALSE is a computationally complete set of operators
2 input memristors and one work memristor can build NAND gate
Having NAND we are creating a link to known logic synthesis algorithms 12

13. Memristors in digital logic
IMPLY and FALSE is a complete set of operations to perform all boolean logic functions
3 memristors can perform a NAND operation p3 p2 p1
Two-input NAND needs three pulses 13

14. Examples of implication uses
((ab)  0) = (a’+b’)
((ab)  (ab)) = (a’+b’) + ab
(0 ab) = (ab)
(a b) = (a’+b)

15. a a + b b a  a a + b b a  ( a + b) = a *  b b a b
All these circuits assume that value of b already exists.
If it does not exist, we need two inverters (from IMPLY) to create it. a
a + b b a
 a
a + b b a
 ( a + b) = a *  b b a b
a +  b = (a * b)

16. a a + b b a  a a + b b a  ( a + b) = a *  b b a b  (a * b)
All these circuits assume that value of b already exists.
If it does not exist, we need two inverters (from IMPLY) to create it. a
a + b b a
 a
a + b b a
 ( a + b) = a *  b b a b
 (a * b)

17. Now we assume that all inputs must be created with Stateful IMPLY technology from scratch.

18. NOT & OR

19. NOT & OR
NOT
OR with two inputs A x A x B A A x x B B

20. NOT A x A x A B C A
NOT is a one WM gate

21. 2-input OR is a two WM gate
X=A+B B B B A B
2-input OR is a two WM gate B
A+B B A

22. NAND & AND
NAND & AND

23. NAND & AND
NAND & AND
NAND A x B A x B

24. 2-input NAND is a one ancilla gate 2-input AND is a two ancilla gate
NAND & AND A B C
NAND(a,b)
2-input NAND is a one ancilla gate
2-input AND is a two ancilla gate
AND(a,b)

25. SOP Two Working Memristors Realization of a Sum of positive Productsb c d
Working (memorizing) memristor
(ba) =b’+a
(c(ba)  c) = (c’+(b’+a)=(bc)’+a
(bcd)’+0
NAND(b,c,d)
bcd+yzv 2 1
SOP
NAND(y,z,v)
Two Working Memristors
Imply serves as inverter y z v
(yzv)’ + 0 2 1
Realization of a Sum of positive Products

26. 2-input INHIBIT is a two WM gate
Inhibit gate
A * B’ = (A’ + B)’
2 gates
2-input INHIBIT is a two WM gate A B C
Two working bits
A’ + B A’
A * B’ = (A’ + B)’ B’

27. NOR Gates

28. NOR
NOR is a two WM bit gate A B C B
(A+B)’ A
A+B A

29. EXOR Gates

30. EXOR = 8 literals in NAND = 8 IMPLYB B’ A’
A + B’ A B
B + A’
A’B B
A’B + A B’
EXOR is a three WM gate A’ A B’

31. SYNTHESIS WITH EXORS WITH NO LIMIT ON NUMBER OF ANCILLA BITS

32. This circuit has 4 working memristors and 16 IMPLY gatesB A
A’B + A B’ A’
A + B’
A’B B’
B + A’
First Working Memristor
Second Working Memristor
Third Working Memristor C
A’B + A B’ A’ A
A + B’
A’B B’ B
B + A’
This circuit has 4 working memristors and 16 IMPLY gates
Fourth Working Memristor
16 IMPLY gates, 4 WM

33. A B B’ A’
A + B’ A B
B + A’
A’B
A’B + A B’

34. MUX

35. MUX is a three ancilla gateB C
AB + A’C A’ A
(A’C)’
(AB)’
(A+C’)’
MUX is a three ancilla gate B A C A’
7 WM expected

36. Circuits from reversible gates versus circuits from memristor material implications
Similarities
Differences
No fanout
In-gate memory exists
No inverter
Different gates

37. Examples of typical multi-input gates

38. Realization of positive product (negated) which is multi-input NANDB C A
A + B
A + B + C = (ABC)

39. Realization of positive product (negated) which is multi-input ORB C
  A
A +   B
A + B +   C

40. Area and Delay Area Delay In CMOS: number of gates
Memristive logic: number of input + work memristors
Delay
In CMOS: number of logic levels
Memristive logic: number of gates + number of FALSE operations 40

41. Our Understanding of Lehtonen’s Algorithm: Synthesis with K-maps41

42. Synthesis with K-maps
21 IMPLY gates, 2 WM 42

43. Variants of synthesis algorithms
Find all groups in every level (Lehtonen).
Find only groups corresponding to essential primes and secondary essential primes.
Find minimum SOP cover of F and SOP cover of F’ and use groups that correspond to primes from these covers.
Use cost heuristics related to best prime selection.

44. Secondary essential primes in red
All primes
Kernels of Primary and Secondary essential primes
Secondary essential primes in red

45. 1 1
All essential primes of F’ in red
All kernels of essential primes of F and F’

46. X X
We take kernel of the first level (in red)
We do not take another kernel of the first level because it was not a kernel of an essential implicant 1 1 1 1 1 X 1 1 X 1 1 1 X 1 1 X 1 1 1 1
We invert the function
We select the group being kernel of essential prime of F’

47. X 1 1 1 1 1 X 1 X 1 1 1 1 X 1 X 1 1 X 1
Replace with don’t cares
We select the group being kernel of essential prime of F’ 1 1 1 X X X 1 X X 1 1 X X X 1 1 X X
Do not select this group
We select the group being kernel of essential prime of F’
We invert the function

48. X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 X 1 X X X 1 X 1 X 1 X 1 X X X
We select the group being kernel of essential prime of F’
We invert the function X X 1 X X 1 X 1 X X X X X X X X X X X X X X X X X 1 X X X X X
We select the group being kernel of essential prime of F’
We invert the function

49. X X 1 X X 1 X 1 X X X X X X X X X X X X X X X X X 1
We select the group being kernel of essential prime of F’
We invert the function X X 1 X X 1 1 X X 1 1 X X 1 X X X X X X X X X 1 X X X X 1 X
Groups selected

50. Number of levels does not count, number of pulses counts to cost
3 pulses each
4 pulses
2 pulses
1 pulse
2 pulses 50

51. Our method replaces primes from minimal cover with bigger positive groups
We have more groups than in SOP
But groups have less literals
We have more inverters for layers
We have no inverters for primes
This tradeoff causes big differences between costs of SOP and our method for various functions
Interesting research topic 1
Groups selected

52. ABC and Automated Logic Synthesis
Can we use existing tools to perform synthesis?
How do we integrate memristor logic to these tools?
Are the results valid with respect to memristor logic specifics (area, delay)? 52

53. ABC From Alan Mishchenko, UC Berkeley
System for synthesis and verification of binary sequential logic circuits
AIG based 53

54. Technology Mapping 54

55. IPMPLY in ABC
Genlib file
Technology Mapping 55

56. ABC Output
Delay is the number of gates + number of memristor initializations
Area is the number of input + work memristors
Cannot be controlled from ABC
One issue that is special in memristor logic: Fanout
Notation
p  q p q
p  q
pq = p  q p q 56

57. Parallel Fanout Green line – previous node will not be overwritten
Red line – previous node will be overwritten
Computing n9 first, overwrites n8
Computing n10 first, overwrites n7
One node (n7 or n8) has to be copied/recomputed

58. Solving Parallel Fanout
What is cheaper?
Copy or recompute?
Which node is cheaper to recompute?
Copying might require one additional work memristor and two pulses
Recomputing n8 requires one pulse
Recomputing n7 requires 4 pulses
Recompute n8

59. Post Processing ABC results
Fanout requires post processing
Two strategies:
Store each value with fanout in an additional memristor (2 inverter)
Recompute the whole sub-circuit that caused fanout
Area/Delay trade-off
Fanout is increasing delay and likely the area as well 59

60. Post Processing ABC results60

61. Benchmarks
For more results, comparison with other SOP and ESOP based methods see poster by Anika Raghuvanshi 61

62. Benchmarks - Notes Pulse Count (Anika)
Solution for minimum number of work memristors (minimum area)
Follows similar approach as presented with the k-maps
Pulse count = delay
Gate count
Number of IMPLY gates as computed by ABC
Can contain fan-out that has to be post-processed
Is not area optimized (more than 2 work memristors)
Pulse Count (ABC)
Post processed to avoid harmful fan-out
Still not area optimized 62

63. Conclusions Very little published on synthesis with IMPLY gates
Very little published on synthesis with memristors.
Although logic synthesis for memristors may seem similar to standard SOP or multi-level combinational synthesis, it is different because of assumption of minimal level number of Working Memristors?
We created methods to synthesize circuits with minimum number of working memristors
We created methods to synthesize circuits with small but not minimal (3, 4) working memristors.
Research question: “how important is this assumption for future memristor technologies?”

64. Future works Synthesize for given fixed number of working memristors
Compare various synthesis methods:
SOP
ESOP
TANT
NAND Tree
Bi-decomposition
Ashenhurst-Curtis decomposition
Analyze tradeoffs between various methods for various types of functions (symmetric, unate, linear, self-dual, etc).

65. Future works Synthesis of pipelined, systolic circuits
Synthesis of Finite State Machines and sequential circuits built from blocks.
Fuzzy and multiple-valued circuits.
Exact synthesis

70. The important characteristic of a memristor is shown in the graph in Figure 2(b), where the steep curve shows the low resistance, as shown by line AB (the ‘on’ state of the memristor) and the flatter curve shows the high resistance (the ‘off’ state of the memristor) as shown by line interval CD.
Memristor’s state described by interval AB can also be called as ‘closed’ or in binary state definitions as ‘1’ or ‘true’.
Similarly, the state described by line interval CD can also be called ‘open’ or in binary state definitions as ‘0’ or ‘false’.
When voltage is increased beyond certain point, shown as Vopen, the state of the memristor changes from closed to open (transition point B to C in the diagram).
Now as the voltage is decreased and goes through the zero point, the resistance stays the same until the negative voltage exceeds Vclose.
At this point the state changes from open to closed (shown by transition from point D to A).

71. If the voltage remains between VClose and VOpen, then there is no change in the state of the memristor.
The change from state open to closed and closed to open, allows memristor to act as a binary switch.
And the fact that the state remains the same when the voltage is between Vopen and Vclose provides the important ‘memory’ property.
Even when the voltage is removed, the state will remain the same, and is remembered.
Observe that while a transistor is a three-terminal device, a memristor is only a two- terminal device which simplifies the layout.

73. As shown in Figure 2(b), Vset is greater that Vclose.
Figure 4(b) shows the circuit when the state of memristor P is ‘1’.
Figure 4: Workings of IMPLY gate using two Memristors. (a) Output when P=0, (b) Output when P=1
Figure 4(a) shows the circuit when the state of memristor P is ‘0’ (open).
P has a high resistance, and can be thought of as disconnected, which implies that the voltage across grounding resistor is zero.
This means that the voltage across the memristor Q is equivalent to Vset.
As shown in Figure 2(b), Vset is greater that Vclose.
The high voltage causes the state of Q to become ‘1’ regardless of Q’s original state (‘0’ or ‘1’).

74. Figure 4(b) shows the circuit when the state of memristor P is ‘1’.
Now P has a low resistance, and can be thought of as a wire, which implies that the voltage across the grounding resistor is now the same as Vcond, the voltage applied at P input.
This means that the voltage across Q is equivalent to Vset-Vcond.
Refering to Figure 2(b) again, the magnitude of Vset-Vcond is less than Vclose, and is not enough to switch the state of Q irrespective of its previous state.
This means that if Q’s state was ‘0’, it will remain ‘0’. If the state was ‘1’, it will remain ‘1’.

75. Logic Synthesis for Memristors
Find all product implicants with positive literals only
Replace with don't care
Invert
Repeat until all '1' covered 75

76. examples ((abc)’+ (ab))’ + (bcd) = ((a’ + b’ + c’) + ab)’ + bcd =
(b’c) + bcd

77. c, Experimental
direct-current current–voltage switching characteristics (four-probe
method).
Traces b–f are offset.
Trace a shows a closed-to-open transition,
trace b shows stability and trace c shows an open-to-closed transition.
Traces d–f repeat this cycle.
d, Switch toggling by pulsed voltages (2 ms long; VSET525V and VCLEAR519 V). Non-destructive reads at 20.2V test the switch state.

78. p q
Figure 2 Illustration of the IMP operation for the four input values of p and q.
a, IMP is performed by
two simultaneous voltage pulses, VCOND and VSET,
applied to switches P and Q, respectively,
to execute conditional toggling on switch Q depending on the state of switch P.
b, The truth table for
the operation q’  p IMP q.

79. c, The blue and red curves show the voltages
Figure 2
c, The blue and red curves show the voltages
applied and the absolute value of the currents read at junctions P and Q
before and after the IMP voltage pulses.
The measured low- and high-current
values reproduce the IMP truth table.