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What would happen if we were to invert everything?
Lecture 8 To date we have concentrated on finding minimum or simplified sum-of-product (SOP) expressions using K maps by looking at terms that give 1s in the output. We can also use K maps to obtain product-of-sums expressions. Consider the normal 3 input K-map. What would happen if we were to invert everything? A B A B C

Using DeMorgan’s theorems what does this simpify to
Then use normal K map methods to get the simplified POS A B A B C A + B A + B C

Exercise 8.1 Use a K map to minimize the following POS expression
(A + B + C) ( A + B + C) (A + B + C ) (A + B + C) (A + B + C) A + B A + B C

Consider the following expression
AB + AC + BC = AB + AC + (A + A)BC … why? = = AB + AC … can you prove this What has happened is that the final term BC has been omitted. The term ‘BC’ is called the consensus of the terms AB and AC. In general, two product terms have a consensus, if there is exactly one variable that appears uncomplemented in one product and complemented in the other.

We now have the interesting situation of being able to remove a whole
product term. We shall prove that both expressions are equal the laws of Boolean algebra (you should also prove it using a suitable truth table).

Examples of consensus and non-consensus terms. Consider each of the
following: A B C D and A B C E F the consensus term _________________ A B C D E and A C E F the consensus term _________________ A B C and A D the consensus term _________________ A B C and B C D the consensus term _________________ B C D and B C D the consensus term _________________

Hazards What are the outputs Y1 and Y2?
The analysis methods we have discussed ignore any circuit delay and predict only the steady-state behaviour - inputs have been stable long time. Because of circuit delays the transient behaviour of a logic circuit may differ from what is predicted by a steady-state analysis. A short pulse, glitch, may be produced and a circuit is said to possess a hazard if it is possible to produce a glitch. Consider the following circuit Y1 What are the outputs Y1 and Y2? A Y2

During the switch, conditions of A=A = 1 or A=A = 0 may exist. Y2
Propagation delay t1 At t=t1, change A from 1 to 0 A A time During the switch, conditions of A=A = 1 or A=A = 0 may exist. Y2 Y1

A static-1 hazard is the possibility of a circuit output producing a 0 glitch when we would expect the output to remain 1 based on static analysis. A static-0 hazard is the possibility of a circuit output producing a 1 glitch when we would expect the output to remain 0 based on static analysis. A source of delays can be through an additional logic gate, especially a NOT gate (since this is single input). This is referred to as the propagation delay of the gate (few ns) 1 ns = s

Consider the following circuit - what can this circuit do????
Consider C to be initially in a HIGH state and A = B = 1. At some time C then goes to 0. There will be a slight delay as the signal propagates thought the NOT gate. The timing diagram is below. A The output Y is A C + B C C B

A B C C Y

When C = 1, NOT C = 0 so Y = 0 . A + 1 . B = B = 1 (since B = 1)
When C = 0, NOT C = 1 so Y = 1 . A B = A = (since A = 1) In both case the overall output is Y = 1. But look what happens at the time of the switch. Here we have a static ‘1’ glitch or hazard. IS there anyway we could predict and eliminate hazards? Y = B Y = A Y

This extra term would be A B.
Lets put the outputs on a K map. There is no single product term that covers both A B C = and A B C = This extra term would be A B. Addition of this extra loop would eliminate the hazard and Y would always be Y = 1 for all times. A B A B C 1

When C = 1, NOT C = 0 so Y = 0 . A + 1 . B + A B = B + A B = 1
Including this extra term the K map would look like this When C = 1, NOT C = 0 so Y = 0 . A B + A B = B + A B = 1 When C = 0, NOT C = 1 so Y = 1 . A B + A B = A + AB = 1 A B A B C 1

Why can we add the extra term…
Look at the new expression for Y Y = A C + B C + A B. Here A B is the Consensus term for A C + B C  It can be added without changing the logic.  Main uses of the consensus term.

The circuit looks like the following
The output is AC + BC + AB A C B

Lecture 9 A static hazard can also be detected algebraically.
Convert the SOP into POS form If the POS contains the sum of a variable and its complement,  static 1 hazard. Consider F = A B + A C = (A B + A)(A B +C ) = (A + A)(B + A)(A + C)(B + C) has a sum (A + A).

Dynamic Hazard In a dynamic hazard  bounce rather than a glitch. Dynamic 0 to 1, the output changes from 0 to 1 to 0 to 1 Dynamic 1 to 0, the output changes from 1 to 0 to 1 to 0 A Function Hazard is one where Two variables are changed at the same time. It cannot be eliminated algebraically

Selecting outputs - Tristate logic and Decoders
Assumed that all logic levels are either 0 or 1 (including Don’t care conditions). Tristate logic gate: output depends on the logic inputs and the value of an enable input. When the enable input is active the gate behaves as normal. When the enable input is not active the gates behaves as if it is not connected (- high impedance Z state).

The truth table for a input A with enable (EN) for tristate inverter would look like

Exercise 9.1 Consider the following circuit
A EN Y B What is Y when EN = 0? What is Y when EN = 1? What does this result mean?

A decoder is a device that when activated selected one of several o/p
Decoders A decoder is a device that when activated selected one of several o/p lines based on a coded input signal. For an n-bit binary number and there are 2n o/p lines. Some (most) decoders also have an enable i/p. The truth table for a active high 2 input decoder is A B 1 2 3

Here the o/p is active HIGH. The decoders just is an AND gate for
each o/p plus 2 NOT gates to invert the inputs. 1 2 3 A B

The active LOW output version looks like
B 1 2 3

Most decoders also have one or more Enable inputs (EN).
- When the input is active the decoder behaves as normal. - When the enable is inactive all the o/p of the decoder are inactive. In most systems with a single enable input the input is active LOW (called EN’)

1 2 3 A B EN’

Exercise 9.2. Write down the truth table for a 2 input active high output decoder with an active low input enable.

Operation When EN’ = 1, a 0 is on the input to each AND gate and this all of the AND gate outputs are 0 When EN’ = 0 the additional input is 1 and then the o/p will be selected by a and b is one as before.

Why do we want active LOW enable.
Active LOW means that the system is on when there is low logic at the input  we get the gate to work by applying no voltage. Question: How then do we switch the system OFF …… We switch the system off when by applying a voltage corresponding to logic 1. So for a system that is largely on most of the time we save on power since we don’t need to take power from lines only from the inverter.

The output of the decoder is the address of the logic gate
The output of the decoder is the address of the logic gate. This is important for ROM memory. It passes no further information. Look at the inputs there no data inputs into the gates only the enable inputs and the address selectors A and B. The opposite to an encoder is decoder.

Encoders The opposite to a decoder is an encoder Used where several devices are generating at once. The truth table for a 4 line (A3-A0) encoder is

How do you distinguish between no device and device A0?
Priority encoders Output is determined by the device with the highest priority Exercise 9.3 Design a priority encoder with 4 active high inputs 0-3 and 3 active high o/p (Z1,Z2, NR). Here NR means no device is requiring service. Input 0 is the highest priority.

1 2 3 Z1 Z2 NR

And now implement this logic on 2 K maps and simplify
Z1 Z2

Summary Static hazards can be removed by using the consensus term Hazards can be detected using the POS representation Tristate logic has an enable input Decoders selected particular output lines. They can pass an address - but carries no other information Encoders are the opposite to a decoder and can have priority.

Lecture 10 A X0 Y X1 Multiplexers If the input to A = 1, then Y = X0

The multiplexer circuit: Two or more signals at different times
 time-division multiplexing. Input A is the addressing input If the A input switches back and forth at a frequency more than double the frequency of either digital signal, both signals will be accurately reproduced.

Common application: Dynamic memory uses the same address lines for both row and column addressing. Multiplexers select the row address to the memory, then switch to the column address. In such an application, this circuit is commonly called a data selector.

Depending on the values of A and B, one of the different inputs X0-X3 will be the output.

What is the significance of A and B?
The Boolean logic expression in this case will be Y = A B X0 + A B X1 + A B X2 + A B X3 We can see that all logic elements of A and B are present so the multiplexer is sometimes called a universal logic block. The Xs are the data entries and A and B are the control lines. What is the significance of A and B?

Consider the function F = A B + A B C + A B C ,
Exercise 10.1 Consider the function F = A B + A B C + A B C , how could this be implemented using a multiplexer using C as the data entry. Step 1 – First expand the product terms present to consist of the maximum number of variables present (in this case 3). F =

Step 2. If A and B are the control lines than F must be expressed as
F = A B X0 + A B X1 + A B X2 + A B X3 In this case the value of data inputs are X0 = X1 = X2 = X3 = There is nothing special about A and B being the control lines.

Exercise 10.2 With the same expression for F and now using A and C as control terms find the appropriate values of B that are to be used for the 4-to-1 multiplexer.

For more complicated structures we can use a K map. For example:
Exercise Implement the Boolean function F= S (0, 1, 3, 6, 7, 8, 11, 12, 14) using an 8 x 1 multiplexer using D as the input variable. If D is the input variable then we are looking for all the 8 possible combinations of A, B and C. e.g is A B C and is A B C etc.

Step 1 Mark 1s in the appropriate square of the K map
A B A B C D 1 Step 2 Group together the 8 ABC terms and write out what the values of D and NOT D are

If both D and NOT D are present (1,1) then the data entry is 1
If neither D nor NOT D is present (0,0) then the data entry is 0 If only one entry is present (either (0,1) or (1,0)) (then term with 1 is the data entry)

For the function F = S (0, 1, 3, 6, 7, 8, 11, 12, 14) we used an 8 x 1 multiplexer. This is better than using a 16 x 1 multiplexer. If we used a 16 x 1 then with D as the input variable we would simply have D0 = 1, D1 = 1, D2 = 0, D3 = 1, D4 = 0, D5 = 0, D6= 1, D7 = 1, D8 = 1, D9 = 0, D10 = 0, D11 = 1, D12 = 1, D13 = 0, D14 = 1, D15 = 0 We got these numbers from the values of D and NOT D in the truth table.

Exercise 10.4 Redo the exercise 10.3 using A as the data inputs and B C D as the control lines. You can use the same K map. Show that the data entry values are (0-7): 1, NOT A, 0, 1, A, 0, 1 and NOT A

Question: If B C and D are the control lines, how would you
represent a term such as B C D on a K map.

The opposite of the multiplexer circuit, is the demultiplexer.
This circuit takes a single data input and one or more address inputs, and selects which of multiple outputs will receive the input signal. Out 1 Y Out 2

A 2-to-4 line decoder/demultiplexer is shown below.
Out 1 IN Out 0 B Out 2 Out 3

Summary A multiplexer is a deice that takes several inputs and puts them onto a single line at different times. What signal is passed is determined by the logic used. For a 4 variable MUX, we can have 16 inputs using 1 and 0s or 8 lines using a single variable or 4 lines using two variables as the data entry. The opposite to a MUX is a demuliplexer.