Presentation is loading. Please wait.

Presentation is loading. Please wait.

Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse.

Similar presentations


Presentation on theme: "Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse."— Presentation transcript:

1 Glitches & Hazards

2 Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse at the output of a combinational circuit Glitches can result from gate delays Glitches depend on the input patterns  glitches may not occur if the input pattern that would cause the glitch never occurs  A circuit with the potential for a glitch has a hazard A circuit with a hazard may or may not glitch

3 Glitch Example  F = AB + A'C: assume all gate delays = 10ns  An input change from ABC = 111 to 011 results in a glitch  output changes from 1  0  1 again A static hazard: result should have stayed statically at 1

4 Static & Dynamic Hazards  Static hazards:  Dynamic hazards: 11  00  10  01 

5 Removing Static Hazards  Glitch occurs in moving from one implicant to another within a cover When two adjacent 1's are not covered by a single implicant Solution: add an extra implicant to provide that coverage  F = AB + A'C + BC No longer minimum form  but no hazard now B C A

6 Hazard Removal: Example  F(A,B,C,D) =  m(6,7,8,9,12,13,14,15)  The red prime implicant removes the static-1 hazard C D A B

7 Dynamic Hazards  Dynamic hazards do not occur in two-level combinational circuits  only in multi-level circuits x 2 x 1 x 3 x 4 b a c d f x 2 x 3 x 4  x 1 b a c d f One gate delay

8 Causes of Dynamic Hazards  For an output to change 0  1  0  1 (i.e. 3 times) in response to a single input change, there must be at least 3 paths of different length in the circuit 2 gate delays: x 1  b  f 3 gate delays: x 1  a  b  f 4 gate delays: x 1  a  c  d  f x 2 x 1 x 3 x 4 b a c d f

9 Removing Dynamic Hazards  Removing dynamic hazards is very difficult  Even detecting dynamic hazards is very difficult  Stick to two level designs to ensure combinational circuits do not have dynamic hazards Sequential circuits do not have this problem

10 Quine-McClusky Method

11  An algorithm that CAD tools can and do use  Uses tables to: Compute all prime implicants Identify essential prime implicants Select the minimum number of prime implicants for a cover  Is based on the combining property again x y + x y' = x (y + y') = x

12 Grouping the Minterms  f(A,B,C,D) =  m(0,4,8,10,11,12,13,15)  Arrange all minterms according to the number of 1’s in the binary representation  Sort and group them  These are called 0-cubes Like vertices of a 4D cube

13 Forming 1-cubes  Compare each 0-cube in one group with each 0- cube in an adjacent group Use combining property to form 1-cubes 0 cubes 00000X 40100X 81000X X X X X X 1 cubes 0,40x00 0,8x000 8,1010x0 4,12x100 8,121x00 10,11101x 12,13110x 11,151x11 13,1511x1

14 Forming 2-cubes  Compare each 1-cube in one group with each 1- cube in an adjacent group Use combining property to form 2-cubes 2 cubes 0,8,4,12xx00 1 cubes 0,40x00X 0,8x000X 8,1010x0 4,12x100X 8,121x00X 10,11101x 12,13110x 11,151x11 13,1511x1 mark each 1-cube that contributes to a 2-cube

15 The Prime Implicants  All “unchecked” cubes are prime implicants They did not get combined into a larger cube 2 cubes 0,8,4,12xx00 1 cubes 0,40x00X 0,8x000X 8,1010x0 4,12x100X 8,121x00X 10,11101x 12,13110x 11,151x11 13,1511x1 0 cubes 00000X 40100X 81000X X X X X X All prime implicants are: P = { 10x0, 101x, 110x, 1x11, 11x1, xx00 }

16 Prime Implicant Cover Table  For each prime implicant, mark all minterms covered by that implicant primeminterms implicants p110x0XX p2101xXX p3110xXX p41x11XX p511x1XX p6xx00XXXX

17 Find Essential Prime Implicants  p6 is an essential prime implicant  minterms 0 and 4 must be covered by p6 Minimum cover C = { p6 } at the moment primeminterms implicants p110x0XX p2101xXX p3110xXX p41x11XX p511x1XX p6xx00XXXX

18 Row Dominance  p2 row dominates p1 since p2 covers everything that p1 covers p1 can be eliminated  Note: we remove the dominated row primeminterms implicants p110x0X p2101xXX p3110xX p41x11XX p511x1XX p5 row dominates p3

19 Column Dominance  Column 11 column dominates column 10 since everything that covers column 10 also covers column 11 Column 11 can be eliminated  Note: we remove the dominating column  We could also have considered p2 and p5 as essential at this point primeminterms implicants p2101xXX p41x11XX p511x1XX column 15 dominates column 13

20 Final Cover  The final cover is C = { p6, p2, p5 }  f = xx x + 11x1 = C'D' + AB'C + ABD primeminterms implicants1013 p2101xX p41x11 p511x1X

21 Another Example  f(A,B,C,D) =  m(0,2,4,5,6,7,8,10,11,12,15) 0 cubes

22 Cubes 2 cubes 0,2,4,60xx0 0,2,8,10x0x0 0,4,8,12xx00 4,5,6,701xx 1 cubes 0,200x0X 0,40x00X 0,8x000X 2,60x10X 2,10x010X 4,5010xX 4,601x0X 4,12x100X 8,1010x0X 8,121x00X 5,701x1X 6,7011xX 10,11101x 7,15x111 11,151x11 0 cubes 00000X 20010X 40100X 81000X 50101X 60110X X X 70111X X X All prime implicants are: P = { 101x, x111, 1x11, 0xx0, x0x0, xx00, 01xx }

23 Cover Table  C = { p6, p7 } since p6 and p7 are essential primeminterms implicants p1101xXX p2x111XX p31x11XX p40xx0XXXX p5x0x0XXXX p6xx00XXXX p701xxXXXX

24 Row Dominance  Row p5 dominates row p4  Row p3 dominates row p2 primeminterms implicants p1101xXX p2x111X p31x11XX p40xx0X p5x0x0XX

25 Column Domination  Column 10 dominates column 2  Column 11 dominates column 15  Final min cover is C = { p6, p7, p3, p5 }  f = xx xx + 1x11 + x0x0 = C'D' + A'B + ACD + B'D' primeminterms implicants p1101xXX p31x11XX p5x0x0XX

26 Handling Don't Cares  f(A,B,C,D) =  m(0,3,10,15) + d(1,2,7,8,11,14)  Don't care conditions are used for creating the prime implicants  Don't care conditions are not used for computing the minimum cover 0 cubes

27 Cubes 0 cubes 00000X 10001X 20010X 81000X 30011X X 70111X X X X 1 cubes 0,1000xX 0,200x0X 0,8x000X 1,300x1X 2,3001xX 2,10x010X 8,1010x0X 3,70x11X 3,11x011X 10,11101xX 10,141x10X 7,15x111X 11,151x11X 14,15111xX 2 cubes 0,1,2,300xx 0,2,8,10x0x0 2,3,10,11x01x 3,7,11,15xx11 10,11,14,151x1x All prime implicants are: P = { 00xx, x0x0, x01x, xx11, 1x1x }

28 Cover Table  Include only required minterms in the initial cover table  There are no essential prime implicants primeminterms implicants p100xxXX p2x0x0XX p3x01xXX p4xx11XX p51x1xXX

29 Branching  There are no dominant rows and no dominant columns  Require a branching strategy Backtracking type algorithm  Select C = { p1 } primeminterms implicants p100xxXX p2x0x0XX p3x01xXX p4xx11XX p51x1xXX

30 Min Cover That Includes p1  Row p5 dominates rows p2, p3, and p4  Min cover C = { p1, p5 }  f = 00xx + 1x1x = A'B' + AC Cost = = 9 primeminterms implicants1015 p2x0x0X p3x01xX p4xx11X p51x1xXX

31 Backtrack  Now backtrack and eliminate p1 to find covers primeminterms implicants p100xxXX p2x0x0XX p3x01xXX p4xx11XX p51x1xXX primeminterms implicants p2x0x0XX p3x01xXX p4xx11XX p51x1xXX Column 10 dominates column 0

32 Min Cover That Excludes p1  Row p4 dominates rows p3 and p5  Min cover C = { p2, p4 }  f = x0x0 + xx11 = B'D' + CD Cost = = 9 Same cost as other solution! primeminterms implicants0315 p2x0x0X p3x01xX p4xx11XX p51x1xX

33 Factoring and Decomposition

34 Factoring  Two level logic is good for problems with only a few variables and/or limited fan-in to all gates Factoring can be used to reduce fan-in, but results in > 2 level logic  Ex: f(A,B,C,D,E,F) = AB'CD'EF + ABC'D'E'F  Requires two 6 input ANDs, one 2 input OR If only 4 input AND gates are available then we can factor f into f(A,B,C,D,E,F) = AD'F(B'CE + BC'E')  Requires one 4 input AND, two 3 input ANDs, one 2 input OR Requires 3 level logic  multi-level synthesis

35 Multi-level Synthesis  If fan-in is limited to at most 4, then the original two level circuit could be done as ….  The factored circuit could be done as … cost = = 21 cost = = 16 cascading ANDs

36 Functional Decomposition  Multi-level circuits may sometimes be preferred over two-level circuits due to reduced cost Done at the expense of longer delays  Decompose circuits into subcircuits with shared functionality Shared subcircuits provide reduced total cost

37 Example Functional Decomposition  SOP form: f = A'BC + AB'C + ABD + A'B'D cost = = inverters + 2 fan-in = 25  factoring … f = (A'B + AB') C + (AB + A'B') D = g C + g' Dwhere g = A'B + AB' since g' = (A'B + AB')' = (A'B)'(AB')' = (A+B')(A'+B) = AA' + B'A' + AB + B'B = AB + A'B'

38 Implemented Decomposition cost = inverters + 3 fan-in = 24

39 Another Example  The shaded region is g(X,W) = XW' + X'W f(V,W,X,Y,Z) = g (V+Y+Z) + g' (V+Y+Z)' = g h + g' h' Y Z W X Y Z W X V = 0 V = 1

40 Implementation cost = = 30 minimal SOP cost = 55 (includes inverters)


Download ppt "Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse."

Similar presentations


Ads by Google