Digital Design – Optimizations and Tradeoffs

Name: Digital Design – Optimizations and Tradeoffs
Uploaded: 2017-10-07T02:41:02+00:00
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Description: Digital Design – Optimizations and Tradeoffs

Digital Design – Optimizations and Tradeoffs
Chapter 6 - Optimizations and Tradeoffs

Digital Design Optimizations and Tradeoffs
Figure 6.1 A circuit transformation that improves both size and delay, i.e., an optimization.

Figure 6.2 A circuit transformation that improves size but worsens delay, i.e., a tradeoff.

Figure 6.3 Optimizations (left) versus tradeoffs (right).

Figure 6.4 Three-variable K-map.

Figure 6.5 Minimizing a three-variable function using a K-map.

Figure 6.6 Four adjacent 1s. Figure 6.7 Non-optimal circles.

Figure 6.8 Four adjacent 1s. Figure 6.9 Circling a 1 twice.

Figure 6.10 An unnecessary term. Figure 6.11 Sides are adjacent.

Figure 6.12 Invalid circle. Figure 6.13 Four adjacent 1s.

Figure 6.14 Four-variable K-map.

Figure 6.15 Eight adjacent cells.

Figure 6.16 w’xz and yz terms.

Figure 6.17 Terms on the K-map. Figure 6.18 A cover.

Figure 6.19 K-map example.

Figure 6.20 Map with don’t cares. Figure 6.21 Wasteful use of X’s.

Figure 6.22 Sliding switch example. Figure 6.23 Without don’t cares. Figure 6.24 With don’t cares.

Figure 6.25 A cover is not necessarily optimal -- the top cover uses more terms.

Figure 6.26 Implicants. Figure 6.27 Essential prime-implicants.

Table 6.1 Heuristic for two-level logic size optimization starting with a K-map.

Figure 6.28 All prime implicants (top); including essential prime implicants in the cover (middle); covering remaining 1s (bottom).

Figure 6.30 Multi-level logic to tradeoff performance and size: (a) two-level circuit, (b) multi-level circuit with fewer transistors, (c) illustration of the size versus delay tradeoff. Numbers inside gates represent transistor counts.

Figure 6.31 Multi-level logic to tradeoff performance and size: (a) two-level circuit, (b) multi-level circuit with fewer transistors, (c) tradeoff of size vs. delay. Numbers inside gates represent transistor counts.

Figure 6.32 Multi-level optimization that reduces size without increasing delay, by altering a non-critical path: (a) original circuit, (b) new circuit with fewer transistors but same delay, (c) illustration of the size optimization with no tradeoff with delay.

Figure 6.33 Eliminating redundant states.

Figure 6.34 Laser timer state diagram with alternative binary state encoding.

Table 6.2 State table for laser timer controller with alternative encoding.

Figure 6.35 FSM for given sequence.

Table 6.3 State table using binary encoding. Table 6.4 State table using one-hot encoding.

Figure 6.36 One-hot encoding can reduce delay: (a) minimum binary encoding, (b) one-hot encoding, (c) though total sizes may be roughly equal (one-hot encoding uses fewer gates but more flip-flops), one-hot yields a shorter critical path.

Figure 6.37 One-hot encoding of laser timer.

Table 6.5 State table for laser timer controller with one-hot encoding.

Figure 6.38 FSM for given sequence.

Figure 6.39 Sequence generator FSM.

Table 6.6 Partial state table for sequence generator controller using output encoding.

Figure 6.40 Sequence generator controller with output encoding.

Figure 6.41 Standard controller architecture -- general view.

Figure 6.42 Moore (a) versus Mealy (b) FSM controller architectures.

Figure 6.43 A Mealy FSM associates outputs with transistions, not states.

Figure 6.44 Capturing desired behavior using a: (a) Moore FSM, (b) Mealy FSM.

Figure bit carry-ripple adder, with the longest path (the critical path) shown.

Figure bit adder built from two 4-bit adders.

Figure 6.47 Adding two binary numbers by a naive inefficient carry lookahead scheme -- each stage looks at all earlier bits and computes whether the carry-in bit to that stage would be a 1.

Figure 6.48 Adding two binary numbers using a fast carry-lookahead scheme.

Figure 6.48 Adding two binary numbers using a fast carry-lookahead scheme. (cont.)

Figure 6.49 High-level view of a 4-bit carry-lookahead adder.

Figure 6.50 Gate size problem.

Figure bit adder implemented using four 4-bit adders connected in a carry-ripple manner.

Figure bit adder implemented using four CLA 4-bit adders and a second level of lookahead.

Figure 6.53 Simplified view of multi-level carry-lookahead, showing tree structure, which enables fast addition with reasonable numbers and sizes of gates. Each level adds only two gate-delays.

Figure bit adder block diagram (top left); carry-ripple implementation using two 4-bit adders (top right); carry-select implementation using three 4-bit adders (bottom).

Figure 6.55 Adder tradeoffs.

Figure 6.56 Multiplication done by generating a partial product for each bit in the multiplier (the number on the bottom), accumulating the partial products in a running sum.

Figure 6.57 Internal design of a 4-bit by 4-bit multiplier.

Figure 6.58 FSM describing the controller for the 4-bit multiplier.

Figure 6.59 Non-pipelined versus pipelined datapaths.

Figure 6.60 Pipelined FIR filter.

Figure 6.61 SAD datapath using concurrency for speed, along with the controller FSM.

Figure Two different component allocations: (a) two multipliers, (b) one multiplier, (c) the one multiplier allocation represents a tradeoff of smaller size for slightly more delay.

Figure 6.63 Two different operator bindings: (a) binding 1 uses two muxes, (b) binding 2 uses only one mux, (c) binding 2 represents an optimization compared to binding 1.

Figure 6.64 Scheduling: (a) initial 3-state schedule requires two multipliers, (b) new 4-state schedule requires only one multiplier, (c) new schedule trades off size for delay (extra state).

Figure 6.65 Re-scheduling the FIR filter to reduce the circuit’s size.

Figure 6.66 High-level state machine for serial 3-tap FIR filter. We ignore the writing of the constant registers (c0, c1, c2) for simplicity in the example.

Figure Serial FIR filter datapath.

Figure 6.68 Adder tradeoffs.

Figure 6.69 Searching a sorted memory for the key 0x00000F0A -- linear search requires 97 reads/compares, binary search only 3.

Figure 6.70 Clock gating: the clock signal switches every cycle on all the heavily-bolded wires, but the xt registers are only loaded in state S1, and the yreg in state S5 -- so most of the clock switching is wasted.

Figure 6.70 Clock gating: gating the clock reduces the switching on the clock wires.

Figure 6.71 Using low power gates.

Figure 6.72 Using low-power gates on non-critical paths. Numbers inside a gate represent the gate’s delay in nanoseconds, and the gate’s power consumption in nanowatts.

Digital Design – Optimizations and Tradeoffs

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