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Kailua-Kona, 05.11.2002 Marcel Trimpl, Bonn University Readout Concept for Future Pixel Detectors based on Current Mode Signal Processing Marcel Trimpl.

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Presentation on theme: "Kailua-Kona, 05.11.2002 Marcel Trimpl, Bonn University Readout Concept for Future Pixel Detectors based on Current Mode Signal Processing Marcel Trimpl."— Presentation transcript:

1 Kailua-Kona, Marcel Trimpl, Bonn University Readout Concept for Future Pixel Detectors based on Current Mode Signal Processing Marcel Trimpl Bonn University Vertex 2002Kailua-Kona, November 2002 Bonn University / MPI Munich (HLL) L.Andricek, G.Lutz, P.Lechner, R.H.Richter, L.Strüder P.Fischer, I.Peric, M.Trimpl, J.Ulrici, N.Wermes

2 Kailua-Kona, Marcel Trimpl, Bonn University DEPFET-Performance single-pixel spectra: ENC = 4.8 +/- 0.1 e K low power consumption (< 1W for whole TESLA vtx-sensor) (row-wise operation) spatial resolution: ~ 9µm (with 50x50 µm 2 pixel) ~ 3.2 mm Matrix-picture with 55 Fe: [J.Ulrici, Bonn] fast and low noise readout needed !! excellent energy resolution (low noise needed for thinned detector) thinnable (50µm proposed for TESLA) small pixelsize possible (25x25µm 2 ) good spatial resolution (charge sharing)

3 Kailua-Kona, Marcel Trimpl, Bonn University Proposed concept for TESLA thin detector-area down to 50µm frame for mechanical stability carries readout- and steering-chips first thinned samples: [L.Andricek, MPI Munich] matrix is read out row-wise

4 Kailua-Kona, Marcel Trimpl, Bonn University continue with next row... Collected charge in internal gate ~ (Difference of both currents) Reset one row and measure pedestal currents Select one row via external Gates and measure Pedestal + Signal current Matrixoperation Readout-scheme:Matrix-scheme: Advantages of readout: pedestals need not to be stored 1/f noise is reduced (CDS) But: complete reset (clear) needed

5 Kailua-Kona, Marcel Trimpl, Bonn University Readout Architecture V1.0 Regulated Cascode keeps drain potential constant (Signal+Pedestal) are stored in fast current memory cell (20ns, inverting) Pedestal-Current after Reset is subtracted automatically Hit-Identification with fast current comparator Hit-Information + analog value are stored in mixed-signal FIFO FIFO is emptied row by row Fast digital scanner identifies hits in a row (up to 2 hits per cycle) and multiplexes the corresponding analog currents to the outputs (no external trigger) DEPFET provides current + fast readout needed current readout

6 Kailua-Kona, Marcel Trimpl, Bonn University... and... it is easy to add new features on chip (algorithmic) ADC at the end (only needs to digitize hits – saves power) larger buffer to store several rows at front end possible (if reset is not fast enough) analog signals: row-wise common-mode-rejection reduces common noise pickup remarkably digital signals: neighbour logic (mark neighbour pixel of hit for readout even if they are below threshold) more hit scanners can easily be added (if occupancy is higher than at TESLA)

7 Kailua-Kona, Marcel Trimpl, Bonn University Basic Storage Principle Storage phase: input- and sample-switch are closed. (storage capacitance is parasitic gate-capacitance of nmos) I = I DEPFET + I Bias I DEPFET Transfer phase: Output switch is closed. I DEPFET is flowing out. (done immediately after sampling) Sampling phase: sample and input switch are opened ( voltage at capacitance unchanged current unchanged ) I = I DEPFET + I Bias

8 Kailua-Kona, Marcel Trimpl, Bonn University Prototype-Chip TSMC 0.25 µm process with radiation-tolerant layout contains all basic parts of proposed design (various memory-cells, fast hit-finder, current comparator structures) 1.5mm 4 mm

9 Kailua-Kona, Marcel Trimpl, Bonn University high speed and high accurancy Bandwidth (speed – intrinsically high because of small capacitance) 2. Output conductance (negligible with cascode techniques) 3. charge injection (offset and signal depending) 4. Noise (sampling noise dominant) 5. Radiation tolerant design limits transistor parameters (geometry has to be angular)

10 Kailua-Kona, Marcel Trimpl, Bonn University reduce charge injection If two successive sample-stages are used (like in readout-architecture) the offset is eliminated as well: Iout1 = - Iin + I Iout2 = - Iin + I = Iin + I – I = Iin Use of 2 stages: coarse and fine sampling Error of coarse stage is resampled by fine stage Signal depending charge injection reduced

11 Kailua-Kona, Marcel Trimpl, Bonn University Testsetup for Memory Cells Memory Cell steering U2I I2U U2I ADC input I2U

12 Kailua-Kona, Marcel Trimpl, Bonn University measured linearity 0.1% accurancy 25MHz !! dynamic range depends on bias-current of memory cell (range vs. power) (10µA for DEPFET-readout needed) 2 memory cells with regulated cascode input (like in readout architecture )

13 Kailua-Kona, Marcel Trimpl, Bonn University Bandwith (speed) Simple model: High speed : small C gate, large g m Realistic model: careful design needed to avoid oscillation... Still : small C gate large g m for high speed

14 Kailua-Kona, Marcel Trimpl, Bonn University Noise from current sampling voltage sample-stage: (independent of R Switch ) current sample-stage: Low noise: Large C, small gm (contrary to high speed requirement)

15 Kailua-Kona, Marcel Trimpl, Bonn University sampling noise ~ 30 electrons sampling noise ( assuming g Q = 1nA /e - ) more than other noise contributions (e.g. pmos current source) Noise [ nA] present design ( nA) g m and C Gate are not independent: linked via geometry speed requirement gives ratio (line indicating 50MHz)

16 Kailua-Kona, Marcel Trimpl, Bonn University measured noise low noise expected (< 30 electrons) difficult to measure with simple testsetup cascade of sampling stages on chip corresponds to calculation !!

17 Kailua-Kona, Marcel Trimpl, Bonn University Summary of performance analog part (memory cell): speed: 25MHz accurancy : 0.1 % noise : < 30 electrons very encouraging result digital part: fast hit-finder and current-comparator-block work with desired speed (50MHz)

18 Kailua-Kona, Marcel Trimpl, Bonn University next step.... full 128 channel readout-chip working with DEPFET-Matrix at 50MHz Internal ADC optional Timing at TESLA : 1ms Trainbunch 200ms Trainpause Hits are stored in RAM during train and read out in pause TESLA prototype-system:

19 Kailua-Kona, Marcel Trimpl, Bonn University Summary / Outlook Concept with fast readout for HEP-Experiment (e.g. TESLA) with current mode signal processing presented Architecture of current mode operating prototype-chip has a lot of advantages (low power, high linearity, high speed, wide dynamic range) and is versatile First prototype shows encouraging results with nearly TESLA requirements: Speed has to be improved by better choice of cell parameters : 50MHz possible TESLA Prototype-System working with DEPFET-Matrix expected within 2003


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