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End of Column Circuits Sakari Tiuraniemi - CERN. EOC Architecture 45 9 Ref CLK 40 MHz DLL 32-bit TDC bank address RX 5 TDC bank address RX 5 TDC bank.

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Presentation on theme: "End of Column Circuits Sakari Tiuraniemi - CERN. EOC Architecture 45 9 Ref CLK 40 MHz DLL 32-bit TDC bank address RX 5 TDC bank address RX 5 TDC bank."— Presentation transcript:

1 End of Column Circuits Sakari Tiuraniemi - CERN

2 EOC Architecture 45 9 Ref CLK 40 MHz DLL 32-bit TDC bank address RX 5 TDC bank address RX 5 TDC bank address RX 5 TDC bank address RX PLL 320 MHz 40 registers serial. registers serial. registers serial. registers serial.

3 9 TDCs, each for a group of 5 non-adjacent pixels 32 to 5 bit encoders integrated with hit registers Instead of reading out all the 32 bits Avoid 32x2x9x40 parallel lines in the layout, decrease complexity of the following circuitry Encoders not used in the demonstrator TDC per 5 pixels – EOC TDC 1TDC 2TDC 8TDC 9 address 32 to 5 bit

4 Demonstrator Architecture

5 EOC Demonstrator

6 TDC-bank Hit Registers: layout ready DLL- and TDC-bank Buffers: layout ready DLL VCDL: layout ready CP and PD layout under work Design Status Encoders: not designed 32 to 5 encoder Address encoder Post TDC circuitry: not designed PLL: not designed

7 Delay Locked Loop 32 delay elements 100ps delay each Phase detector Bang-bang detector only gives information of the sign of phase error Charge Pump Adjusts the delay by increasing/ decreasing control voltage by adding/removing charge in C C

8 DLL – Charge Pump Capacitance and current of Charge Pump affects Accuracy of the delay (jitter) Speed of the loop Time to achieve lock Response time for changes (in the clock phase, etc) Need for further simulations to optimize capacitance size against speed 1 st order system - inherently stable loop When higher order poles are at high frequencies

9 DLL – Charge Pump I cp = 1.72 µ A C = 20 pF K vcdl = 1.32 ns/V T = 1/f CLK = 3.2 ns Charge pump current is adjustable Possible to achieve fast locking time with higher current Increase accuracy after lock achieved with lower current T lock = µs I cp = 1.72 µ A From V RFN = 600 mV (down to ~485.7 mV)

10 DLL – Jitter, Transient Analysis Jitter at the last delay element output Δ τ = ps With C = 20 pF I cp = 1.72 µA

11 DLL – Jitter, Transient Analysis Jitter at the last delay element output Δτ = ps With C = 20 pF I cp = 1.72 µA Delay of the last delay element τ = ps ± ps V RFN = 485.7mV ± 0.18 mV

12 DLL – Jitter, Transient Noise Analysis Jitter at the last delay element output Δ τ = ps With C = 20 pF I cp = 1.72 µA

13 DLL – Jitter, Transient Noise Analysis Jitter at the last delay element output Δτ = 18.11ps With C = 20 pF I cp = 1.72 µA Delay of the last delay element τ = ps ± ps V RFN = 493.4mV ± 0.18 mV

14 Status of Work - NEXT 1.Finish layout of DLL 2.Post-layout simulations with DLL and TDC 3.Start design work for PLL and post TDC circuits (shift registers and logic)

15 One delay cell with buffer

16 Delay line

17 D flip flop

18 18 Hit register bank(TDC’s)


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