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Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Embedded Fault Diagnosis.

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Presentation on theme: "Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Embedded Fault Diagnosis."— Presentation transcript:

1 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Embedded Fault Diagnosis for Digital Logic Exploiting Regularity R. Kothe, H. T. Vierhaus Brandenburg University of Technology Cottbus Computer Science Department Computer Engineering Group

2 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Outline 1.Introduction: Fault Diagnosis - when and what for? 2.Scan Test and Pattern Compaction 3.How Fault Diagnosis is Done 4.Embedded Fault Diagnosis Based on Regularity 5.Summary and Conclusions

3 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan Introduction Fault diagnosis becomes a must for production test of ICs and for self-test in the field.

4 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Test-Technology-Traditionally Prototype test Production test In-field test Time Cost Quantity Destructive often never never Diagnosis yes hardly little hours to days seconds to minutes seconds to minutes $ cents to a few $ (none) 5 to 100 thousands to millions (individual test)

5 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Test Technology for Nano-Technologies Prototype test Production test In-field test Time cost quantity Destructive often never never Diagnosis yes yes, must be yes, must be hours to days seconds to minutes seconds to minutes $ cents to a few $ (none) 5 to 100 thousands to millions (individual test) for yield optimization for self-repair for repair

6 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 New Problems with Nano-Technologies Light source mask (reticle) wafer resist exposed resist Wave length: 193 nm Feature size: down to 45 nm

7 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Layout Correction Modified layout for compensation of mapping faults Compensation is critical and non-ideal Faults are not random but correlated ! Requires fast fault diagnosis

8 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Built-in Self Repair (BISR) f Logic blocks r backup / replacement blocks Logic test must identify the faulty block before repair / replacement ! Problem: There is no powerful test machine available !

9 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Why Diagnostic Test is Needed Traditional IC production test does not care for fault diagnosis. Fabrication in nanometer technologies uses exposure wavelengths that are up to5 times longer than the minimum feature size. All layout features need an advanced correction to compensate for mapping faults. This correction is non-ideal. Diagnostic test is required to find faulty layout corrections for fast ramp up in production yield. Built- in Self Repair (BISR) for long-time dependable systems requires built-in diagnostic test as a pre-condition!

10 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Basic Questions Can diagnosis be done on top-of production test technology with massive test data compression ? How good can the diagnostic resolution be ? Is a fine – grain diagnosis as a pre-condition for built- in self repair possible in the field at reasonable cost / overhead ? Note: All answers are yes for regular structures such as memory blocks ! Can production test technology be compatible with in-field testing ?

11 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan Scan Test and Pattern Compaction The workhorse of test technology has to do a variety of jobs never thought of by the it inventors.

12 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Scan-Based IC Test

13 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Essentials of Scan Testing Multiple scan paths (100 to 1000). No whatsoever usage of functional features. Scan path allocation / partitioning without making any use of logic regularity. Test sets are strictly minimized, no specific patterns for fault diagnosis. Fault diagnosis has to come combined with or on top of compaction mechanisms. Identical problems for compaction / diagnosis for external test or built-in self test (logic BIST).

14 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Multi-Scan Path IC Test Pattern Generator (LFSR ) control Multiple parallel scan paths MISR Compacted testresponse ExternalTester Test Processor encodedtest patterns (optional for embedded scan test) Pattern Memory

15 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Data Compression / Compaction Pattern Generator (LFSR ) control Multiple parallel scan paths Time comp. (MISR) ExternalTester Test Processor encodedtest patterns ATPG COMPCOMP Off-line Compaction rate: Space Compactor (XOR-tree) Compaction rate: Pattern Memory On-line

16 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Advanced Scan Test Requirements Fast scan-test for production test without fault diagnosis. Fast scan test for production with additional (off-line) fault diagnosis. Scan output analysis with detailed on-chip diagnosis for silicon debug. Scan output analysis with high-resolution diagnosis as a pre-process for logic self repair. Diagnosis may be done: In parallel with fault detection Selectively after fault detection Encoding / parity bits? MISR-based compaction and analysis?

17 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan How Fault Diagnosis is Done Fault Diagnosis has to be combined with test output compaction / compression. Compaction can be done in space and in time, but loss of diagnostic information is a problem.

18 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Space-Compaction and Fault Masking Comb. Logic (pseudo-) inputs (pseudo-) outputs Input vector Output vector out Avoid multiple output paths by ATPG! f f fault Fault is absorbed Remedy:

19 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Fault Detection by Direct Comparison Comb. logic (pseudo-) inputs (pseudo-) outputs Input vector Scan path clock Ref-Pattern Good outputs ordered, number of appearances noted C O M P A R E Test Processor Ref-out ordered by good response Compare upon detected fault fault

20 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Error Detection Using Compressed Outputs

21 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 MISR-Based Compaction in Time A multi-input signature register (MISR) can do a compaction in time. FF In case of multiple fault events, fault masking is also possible due to aliasing errors.

22 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Diagnosis by Variable MISR Allocation

23 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Coding-Based Diagnosis ScanInput Generator (De-Compactor) &&&&&&& MISR d 0 d 1 d 3 d 4 d 5 d 6 d 2 storage scanclock Backup MISR Read-out for external analysis Code-word Application of multiple code-words to the same scan output

24 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Top Compaction & Diagnosis Technologists Janusz Rajski (Mentor Graphics, formerly PUT) and Jerzy Tyszer ( PUT) Michael Gössel, Jan Rzeha (Univ. of Potsdam) Ralf Pöhl, Andreas Leininger (Infineon Technologies, Munich)

25 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Coding-Based Diagnosis Patented by Infineon Technologies AG and U. Potsdam, 2004

26 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 How the Scheme Works In the normal test mode, all d-inputs are set to 1. The MISR will indicate that a fault has occurred after compaction of one or more full test responses. In the diagnosis mode, the test for the faulty vector is re-applied again. Then the output is encoded in k steps with k being the number needed to implement a fault detecting code for the n scan path outputs. For collecting the diagnosis output, the MISR is operated as a shift register without feedback. The d-inputs are set according to the rules of the code. After k cycles of a local MISR clock, the diagnosis information is stored in the MISR / shift register. Using a Hamming code, an XOR-comparison between the actual output and a reference output directly reveals the faulty scan chain.

27 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Output Encoding d0 d1 d2 d3 d4 d5 d6 d Coding Test-Output MISR (errorcode) & Error det.codes, widthdepending onthenumber ofscanchainsand thediagnostic resolution! Analysis Errorcodingisthesame foreverytestpattern ! Theresultcanalsoaccommodatemultiplefaults!

28 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Features and Limitations Multiple faults can be diagnosed, depending on the code applied. In case of Hamming code, faults that are related to a diagonal in the d-matrix cannot be resolved. The set of d-bits used for encoding is independent of the test output. It can be stored locally and is applied repeatedly. The reference pattern for detection of the faulty output bit needs to be supplied for every bit output vector. In this version, the scheme cannot yet handle undetermined scan outputs.

29 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 The X Output Problem Test responses in scan test may include undetermined output values. Most compaction schemes cannot handle X-bits, but need to replace them by deterministic settings. The information which output bit on which scan chain needs to be set, can be as large as the (compressed) input pattern file itself !

30 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Encoding Test Outputs ScanInput Generator (De-Compactor) scanclock Encoder / Compactor Code- bits X-blanking information Signature Multiple parallel scan paths

31 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan Embedded Fault Diagnosis Built-in self repair needs to be done in the field with limited resources for test and diagnosis.

32 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Built-in Fault Diagnosis? ScanInput Generator (De-Compactor) &&&&&&& MISR compare d 0 d 1 d 3 d 4 d 5 d 6 d 2 d-value storage scanclock MISRclock: k *scan-clock a Stop /activateMISRfeedback Test Processor Pattern- ROM RAM 16 Ref. MISR Ser. / parallel load

33 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 No Solution for Embedded Diagnosis? For efficient diagnosis by as-few- as- possible parity bits, long registers / MISRs are required ( bits!) A reference MISR is needed in order to detect the clock cycle at which a specific scan path had a fault. The diagnosis reference patterns must either be stored and supplied (e.g. one for every test pattern). A workable solution for a few specific tests, but not in the general case!

34 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Regularity in Logic Designs Scan paths and MISR sections are associated with equal structural entities.

35 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Regularity in Test Generation Equal sections can be fed in parallel with the same test patterns. LFSR control M1 1 M1 2 M2 1 M2 2 M3 1 M3 2 M3 3 Simplified ATPG, smaller and faster pattern input compaction circuitry! scan- path

36 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Fault Diagnosis by Virtual Majority Vote

37 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Registration of Fault Events

38 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Single / Double Fault Events Unit single fault Unit double fault Unit double fault Unit double fault

39 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Triple Fault Events Unit triple fault Unit triple fault Unit triple fault doublesingle Unit triple fault

40 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Usage for Built-in Self Repair? Designs that facilitate built-in self repair will be composed from a limited number of different functional units (NAND, NOR, FF) have internal redundancy. Logic will become regular!

41 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Signal Processing Architecture Z -1 Z -1 Z -1 Z -1 Z -1 Z -1 Z -1 Z -1 x x x x x x x xx x x c 0 c 1 c 2 c 3 c M-1 c M d 1 d 2 d 3 d N-1 d N x (n) Input Output y (n) Verzöge- rungen y (n-1) y (n-2) y (n-3) y (n-N-1) y(n-N) x(n-1) x(n-2) x(n-3) x(n-M-1) x(n-M) Addierer Multipliz. Z -1 Z -1 Z -1 Z -1 Z -1 Z -1 Z -1 Z -1 x x x x x x x xx x x c 0 c 1 c 2 c 3 c M-1 c M d 1 d 2 d 3 d N-1 d N x (n) Input Output y (n) Verzöge- rungen y (n-1) y (n-2) y (n-3) y (n-N-1) y(n-N) x(n-1) x(n-2) x(n-3) x(n-M-1) x(n-M) Addierer Multipliz.... are typically regular by nature!

42 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan Summary and Conclusions Fault diagnosis becomes an indispensable part of test. Fault diagnosis for highly irregular logic structures becomes expensive. DSP architectures and re-configurable logic architectures are inherently regular. Exploiting regularity for test generation and for fault diagnosis can reduce the need for reference outputs significantly, facilitating embedded fault diagnosis. Strongly correlated faults need reference data!

43 Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 What Else?? Thank You for Your Attention!! There is still a lot of work to do before we will have highly dependent nano-electronic circuits and systems.


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