Presentation on theme: "Reliable Data Processor in VLSI"— Presentation transcript:
1Reliable Data Processor in VLSI Senior Capstone ProjectPresented By Rahul ChopraMay 7th 2002Advisor: Dr. Vinod PrasadAbstract:The Reliable Data Processor in VLSI is a user driven data processor that carries out Arithmetic and Logic operations such as AND, OR, XOR, NAND and ADD on 4-bit data. The basic system consists of a 4-bit ALU controlled by a user driven controller. The system has feedback capabilities and receives feedback from an external reliable chip indicating any erroneous data transfer. Applications of the data processor include Digital Signal Processing and data encryption.
2Overview Functional Description Block Diagram Subsystems Controller (3*8 Decoder)7 bit EncoderData Registers, D-FF with Set/ResetALUP-Spice ResultsExpo VHDL/FPGA ImplementationConclusions/Future Developments
3Functional Description 3-Bit User Input to ControllerDecodes User input, Controls ALUALU-Boolean and Arithmetic Operations on 4-bit data arrays.Encoder: 4 Bits From ALU+3 Parity Bits,7-bit OutData Registers-7 D-FF’s, Store Output
4External Error Detection/Reliable Block DiagramExternal Error Detection/ReliableChipFeedbackControllerUserSelect LinesD0D4EncoderALUDataRegistersInput Data4 bit Vectors7-Bit Out
8Registers Clock Input controlled. Feedback from external chip supplies clock input.D-FF’s will store, send data accordingly.Designed Using 7 D-FF’sD-FF’s Individually Built and Tested in Logic Works and L-Edit using NAND, NOT, OR Gates.D-FF’s with Set/Reset capabilitiesSet has Higher Priority
9Registers-D-FF’s with Set/Rst Logic Works Design and Timing
16P-Spice Simulation Results-1 NAND Function of ALUD3 High, Input Vectors NAND 1100ALU Output 0011Out3Out2Out1Out0D3
17P-Spice Simulation Results-2 ADD Function of ALUVectors ADD 1111 , D4 = 1ALU Results - Carry Flag-1, Bits-1010CarryOut3Out2Out1Out0D4
18P-Spice Simulation Results-3 Encoded Data for ALU Adder OperationALU 4 Bit Output , Encoded OutOut7Out6Out5Out4Out3Out2Out1
19Completed System Controller ALU Input Data=> ALU Out Registers/OutputEncoder
20Expo 2002 VHDL code written. FPGA Implementation on XC4000 chip. Presented at Student Expo on April 12th.
21Conclusions/Future Developments Design Tested Successfully using P-Spice.P-Spice cannot handle Changing Inputs, Convergence Problems Nodes approx.Future Developments:MOSIS Fabrication of Design.Testing with error detection chip.More Arithmetic OperationsExpansion to 16/32 bit ALUApplications in Digital Signal Processing/Data Encryption