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Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt1 Lecture 31 System Test (Lecture 22alt in the Alternative Sequence) n Definition n Functional.

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Presentation on theme: "Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt1 Lecture 31 System Test (Lecture 22alt in the Alternative Sequence) n Definition n Functional."— Presentation transcript:

1 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt1 Lecture 31 System Test (Lecture 22alt in the Alternative Sequence) n Definition n Functional test n Diagnostic test  Fault dictionary  Diagnostic tree n System design-for-testability (DFT) architecture  System partitioning  Core test-wrapper  DFT overhead n Summary

2 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt2 A System and Its Testing n A system is an organization of components (hardware/software parts and subsystems) with capability to perform useful functions. n Functional test verifies integrity of system:  Checks for presence and sanity of subsystems  Checks for system specifications  Executes selected (critical) functions n Diagnostic test isolates faulty part:  For field maintenance isolates lowest replaceable unit (LRU), e.g., a board, disc drive, or I/O subsystem  For shop repair isolates shop replaceable unit (SRU), e.g., a faulty chip on a board  Diagnostic resolution is the number of suspected faulty units identified by test; fewer suspects mean higher resolution

3 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt3 System Test Applications A Application Functional test Diagnostic test Resolution Manufacturing Yes LRU, SRU Maintenance Yes Field repair LRU Shop repair SRU LRU: Lowest replaceable unit SRU: Shop replaceable unit

4 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt4 Functional Test n All or selected (critical) operations executed with non-exhaustive data. n Tests are a subset of design verification tests (test- benches). n Software test metrics used: statement, branch and path coverages; provide low (~70%) structural hardware fault coverage. n Examples:  Microprocessor test – all instructions with random data (David, 1998).  Instruction-set fault model – wrong instruction is executed (Thatte and Abraham, IEEETC-1980).

5 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt5 Gate-Level Diagnosis e d a b c T3 T1 T2 T4 a b c Stuck-at fault tests: T1 = 010 T2 = 011 T3 = 100 T4 = 110 Logic circuit Karnaugh map (shaded squares are true outputs)

6 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt6 Gate Replacement Fault e d a b c T3 T1 T2 T4 a b c Stuck-at fault tests: T1 = 010 (pass) T2 = 011 (fail) T3 = 100 (pass) T4 = 110 (fail) Faulty circuit (OR replaced by AND) Karnaugh map (faulty output: red sqaure is 1 output)

7 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt7 Bridging Fault e d a b c T3 T1 T2 T4 a b c Stuck-at fault tests: T1 = 010 (pass) T2 = 011 (pass) T3 = 100 (fail) T4 = 110 (pass) Faulty circuit (OR bridge: a, c) Karnaugh map (red squares are faulty 1 outputs) a+c

8 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt8 Fault Test syndrome t 1 t 2 t 3 t 4 No fault a 0, b 0, d 0 a 1 b 1 c 0 c 1, d 1, e 1 e 0 Fault Dictionary a 0 : Line a stuck- at-0 t i = 0, if Ti passes = 1, if Ti fails

9 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt9 Diagnosis with Dictionary Fault Test syndrome Diagnosis t 1 t 2 t 3 t 4 OR AND e 0 OR-bridge (a,c) b 1 OR NOR c 1, d 1, e 1, e 0 Dictionary look-up with minimum Hamming distance

10 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt10 Diagnostic Tree T4 T1 T2 T3 No fault found T3 T2 b1b1 a1a1 c 1, d 1, e 1 a 0, b 0, d 0 e0e0 c0c0 Pass: t 4 =0 Fail: t 4 =1 a 0, b 0, d 0, e 0 a 1, c 1, d 1, e 1 OR AND OR bridge (a,c) OR NOR

11 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt11 System Test: A DFT Problem n Given the changing scenario in VLSI:  Mixed-signal circuits  System-on-a-chip  Multi-chip modules  Intellectual property (IP) cores n Prepare the engineer for designing testable, i.e., manufacturable, VLSI systems.

12 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt12 Conventional Test: In-Circuit Test (ICT) n A bed-of-nails fixture provides direct access to each chip on the board. n Advantages: Thorough test for devices; good interconnect test. n Limitations:  Works best when analog and digital functions are implemented on separate chips.  Devices must be designed for backdriving protection.  Not applicable to system-on-a-chip (SOC). n Disadvantages:  High cost and inflexibility of test fixture.  System test must check for timing.

13 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt13 PCB vs. SOC n Tested parts n In-circuit test (ICT) n Easy test access n Bulky n Slow n High assembly cost n High reliability n Fast interconnects n Low cost n Untested cores n No internal test access n Mixed-signal devices PCB SOC

14 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt14 Core-Based Design n Cores are predesigned and verified but untested blocks:  Soft core (synthesizable RTL)  Firm core (gate-level netlist)  Hard core (non-modifiable layout, often called legacy core) n Core is the intellectual property of vendor (internal details not available to user.) n Core-vendor supplied tests must be applied to embedded cores.

15 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt15 Partitioning for Test n Partition according to test methodology:  Logic blocks  Memory blocks  Analog blocks n Provide test access:  Boundary scan  Analog test bus n Provide test-wrappers (also called collars) for cores.

16 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt16 Test-Wrapper for a Core n Test-wrapper (or collar) is the logic added around a core to provide test access to the embedded core. n Test-wrapper provides:  For each core input terminal  A normal mode – Core terminal driven by host chip  An external test mode – Wrapper element observes core input terminal for interconnect test  An internal test mode – Wrapper element controls state of core input terminal for testing the logic inside core  For each core output terminal  A normal mode – Host chip driven by core terminal  An external test mode – Host chip is driven by wrapper element for interconnect test  An internal test mode – Wrapper element observes core outputs for core test

17 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt17 A Test-Wrapper Wrapper test controller Scan chain to/from TAP from/to External Test pins Wrapper elements Core Functional core inputs Functional core outputs

18 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt18 Overhead of Test Access n Test access is non-intrusive. n Hardware is added to each I/O signal of block to be tested. n Test access interconnects are mostly local. n Hardware overhead is proportional to: (Block area) – 1/2

19 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt19 Overhead Estimate Rent’s rule: For a logic block the number of gates G and the number of terminals t are related by t = K G  where 1 ≤ K ≤ 5, and  ~ 0.5. Assume that block area A is proportional to G, i.e., t is proportional to A 0.5. Since test logic is added to each terminal t, Test logic added to terminals Overhead = ──────────────────── ~ A –0.5 A

20 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt20 DFT Architecture for SOC User defined test access mechanism (TAM) Module 1 Test wrapper Test source Test sink Module N Test wrapper Test access port (TAP) Functional inputs Functional outputs Func. inputs Func. outputs SOC inputs SOC outputs TDI TCK TMS TRST TDO Instruction register control Serial instruction data

21 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt21 DFT Components n Test source: Provides test vectors via on-chip LFSR, counter, ROM, or off-chip ATE. n Test sink: Provides output verification using on-chip signature analyzer, or off-chip ATE. n Test access mechanism (TAM): User-defined test data communication structure; carries test signals from source to module, and module to sink; tests module interconnects via test-wrappers; TAM may contain bus, boundary-scan and analog test bus components. n Test controller: Boundary-scan test access port (TAP); receives control signals from outside; serially loads test instructions in test-wrappers.

22 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt22 Summary n Functional test: verify system hardware, software, function and performance; pass/fail test with limited diagnosis; high ( ~100%) software coverage metrics; low ( ~70%) structural fault coverage. n Diagnostic test: High structural coverage; high diagnostic resolution; procedures use fault dictionary or diagnostic tree. n SOC design for testability:  Partition SOC into blocks of logic, memory and analog circuitry, often on architectural boundaries.  Provide external or built-in tests for blocks.  Provide test access via boundary scan and/or analog test bus.  Develop interconnect tests and system functional tests.  Develop diagnostic procedures.


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