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VLSI TESTING MEMORY BIST by: Saeid Hashemi Mehrdad Falakparvaz.

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Presentation on theme: "VLSI TESTING MEMORY BIST by: Saeid Hashemi Mehrdad Falakparvaz."— Presentation transcript:

1 VLSI TESTING MEMORY BIST by: Saeid Hashemi Mehrdad Falakparvaz

2 1) : WHAT IS BIST ? n BIST (Built-In Self-Test) : is a design technique in which parts of a circuit are used to test the circuit itself. –Hardcore : Parts of a circuit that must be operational to execute a self test n BIST categories : n Memory BIST n Logic BIST n Logic + Embedded memory (ASICs) n Applications : Mission-critical sytems, self- diagnostic circuitry (consumer electronics).

3 2) : BIST Concepts n BIST Techniques n Test Pattern Generation Techniques (TPG) n Test Response Compression Techniques

4 3 ) BIST Techniques n The BIST techniques are classified bassed on the operational condition of the circuit under test (CUT): n Off-Line BIST n On-Line BIST

5 3-1) : On-Line BIST n Testing occures during normal functional operating conditions (No test mode, Real-Time error detection). n Concurrent :Occures simultaneously with normal functional operation (Realized by using coding techniques). n Nonconcurrent : Carried out while in idle state (Interruptible in any state, realized by executing diagnostic software/firmware routines).

6 3-2) : Off-Line BIST n Deals with testing a system when it is not carrying out its normal functions (Test mode, Non-Real-Time error detection). n Testing by using either on-board TPG + Output Response Analyzer (ORA) or Microdiagnostic routines. n Structural : Execution based on the structure of the CUT(Explicit fault model - LFSR,...). n Functional : Running based on functional description of CUT(Functional fault model - Diagnostic software).

7 4) : Test Pattern Generation Techniques n Exhaustive : Applying all 2**n input combinations, generated by binary counters or complete LFSR. n Pseudoexhaustive : Circuit is segmented & each segment is tested exhaustively(Less no. of tests required): n Logical segmentation : Cone + Sensitized-path n Physical segmentation

8 4 ) : Test Pattern Generation Techniques (Cont.) n Pseudorandom : Not all 2**n input combinations, Random patterns generated deterministically & repeatably, pattern with/without replacement, applicable to both combinational and sequential circuits. n weighted : Non-uniform distribution of 0’s & 1’s, improved fault coverage, using LFSR added with combinational circuits. n Adaptive : Using intermediate results of fault simulation to modify 0’s & 1’s weights, more efficient,more hard ware complexity.

9 5) : Test Response compression techniques n Response compression : A process to form a “signature” from complete output responses. –Signature : Compressed form of saved test results. –Alias : Errorous output when faulty & fault-free sig. are the same. n Compression procedure : Composition of test vector applying, results storing and comparision of the faulty & faultfree signatures. n Compression of : –Simple hardware implementation. –Small performance degradation - No effect on normal circuit behaviour (delay, execution time). –High degree of compression - Signature lenghts to be a logarithmic factor of responses lenghts. –Small aliasing errors.

10 5) : Test Response compression techniques (cont.) n Compression problems : –Existing aliasing errors. –Calculating the good circuit signature. n Calculation of good circuit signatures : –Golden Unit : Applying the test to good part of the CUT. –Simulation : Simulating the CUT and making sure of having good signature. –Fault Tolerant : Producing copies of CUT and conclude the correct signature by finding the subset which generates the same signature.

11 5) : Test Response compression techniques (cont.) n One’s count : The no. of times when 1 occurs in each output (counter). n Transition count : The no. of transitions(0 =>1,1=>0) in the output (XOR +counter). n Parity checking : The parity of response string, 0 if even & 1 if odd (XOR + D-FF). n Syndrome checking : the normalized no. of 1’s inoutput string (k/2**n when k is no. of minterms in an n input circuit), (All possible combination tests). n Signature analysis : Based on redundancy checking (LFSR).

12 6) : Factors affecting the choice of BIST 6) : Factors affecting the choice of BIST n Degree of test parallelism n Fault coverage n Level of packaging n Test time n Complexity of replaceable unit n Factory and field test-and-repair strategy n Performance degradation n Area overhead

13 6-1) : Advantages n Lower cost of test n Better fault coverage n Possibly shorter test times n Tests can be performed throughout the operational life of the chip

14 6-2) : Disadvantages n Silicon area overhead n Access time n Requires the use of extra pins n Correctness is not assured

15 7) : BIST key elements n Circuit under test (CUT) n Test pattern generators (TPG) n Output response analyzer (ORA) n Distribution system for data transmission between TPG, CUT and ORA n BIST controller

16 8) : Specimen BIST architecture Chip, Board or System DISTDIST CUT DISTDIST ORA BIST controller TPG

17 9) : Memory BIST n Memory types –SRAM,DRAM,EEPROM,ROM n Fault models –SAF,TF,CF,NPSF,AF n Test algorithms n Test categories

18 9-1) : Fault models n Stuck-At Fault (SAF) –The logic value of a cell or a line is always 0 or 1 n Transition Fault (TF) –A cell or a line that fails to undergo a 0=>1 or a 1=>0 transition n Coupling Fault (CF) –A write operation to one cell changes the content of a second cell

19 9-1) : Fault models cont. n Neighborhood Pattern Sensitive Fault (NPSF) –The content of a cell, or the ability to change its content, is influenced by the contents of some other cells in the memory n Address Decoder Fault (AF) –Any fault that affects address decoder –With a certain address, no cell will be accessed –A certain cell is never accessed –with a certain address,multiple cells are accessed simultaneously –A certain cell can be accessed by multiple addresses.

20 9-2) : Memory test algorithms n Traditional tests n zero-one,checkerboard,GALPAT,Walking 1/0,Sliding Diagonal,Butterfly n March tests : Tests for stuck-at,transition and coupling faults n MATS,Marching1/0,March X,... n Tests for neighborhood pattern sensitive faults (NPSF)

21 9-3) : Memory test categories n DC : Tests to verify analog parameters n Open/short -Power consumption-leakage,threshold,... n AC : Tests to verify timing parameters n Signal rise/fall time, Setup/hold time, Delay, Access time,. n Dynamic tests : Detects dynamic faults affecting CUT(Recovery, refresh line stuck-at, bit-line precharge voltage imbalance, …)

22 10) : Advanced Topics n Built-In Self-Repair(BISR). n Programmable memory BIST n Generalized Linear Feedback Shift Registers(GLFSR) for pseudo random memory BIST n Transparent BIST for RAMs. n And....

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