# 2015-4-13 Based on text by S. Mourad "Priciples of Electronic Systems" Digital Testing: Design Representation and Fault Detection

## Presentation on theme: "2015-4-13 Based on text by S. Mourad "Priciples of Electronic Systems" Digital Testing: Design Representation and Fault Detection"— Presentation transcript:

2015-4-13 Based on text by S. Mourad "Priciples of Electronic Systems" Digital Testing: Design Representation and Fault Detection http://www.talikom.com.my/tester4.jpg

Copyright(c)2001, Samiha Mourad2 Outline Design Representation Models Switching functions Sensitized Path Boolean Difference Fault Detection and Redundancy Finite State Machines Tabular Representation Binary Decision Diagrams

Copyright(c)2001, Samiha Mourad3 Design Paradigm The design representation space consists of domains and levels Behavioral domain most abstract Structural domain specifies the architecture Physical domain include the transistors and layout

Copyright(c)2001, Samiha Mourad4 Domains and Levels Table 3.1 Domains and Level of Design D o m a i n BehavioralStructuralPhysical System System SpecificationsBlocksChip RTL RTL SpecificationsRegistersMacro Cells Logic Boolean FunctionsLogic GatesStandard Cells L E V E L S Circuit Differential EquationsTransistorsMasks

Copyright(c)2001, Samiha Mourad5 Domains a = b+c z = !(a·d) Behavioral Domain Structural Domain Physical Domain b c d a z b c d

Z(x) - logic function of circuit N x - input vector t - a specific input (test) vector N f - a faulty circuit (N changes as a result of fault f) Fault detection and redundancy Definition: A test vector t detects a fault t iff Z f (t)  Z(t)

0 1 OR 1 x1 x2 x3 0 1 Z1 Z2 Example : OR bridging fault between x1 and x2 Consider test t = 011 Fault detection and redundancy

Example : Z 1 = x1 x2, Z 1f = x1 + x2 Z 2 = x2 x3 Z 2f = (x1 +x2) x3 Z (011) = 01, Z f (011) = 11 => t = 011 detects f The set of all tests that detect f is given by Z(x)  Z f (x) =1 Fault detection and redundancy 0 1 OR 1 x1 x2 x3 0 1 Z1 Z2

X100101XXX100101XX Stuck-at-0 fault 1/0 Fault activation Path sensitization Primary inputs (PI) Primary outputs (PO) Combinational circuit 1/0 Fault effect

1= x 1= y w f c/0 x y 0 = w f c/0 Example: Test for c/0 is w, x, y = 0,1,1 · Activate Fault c/0 · Set x = y = 1 to make c = 1 in Fault-free Circuit · Propagate Value on c to f · Set w = 0 to sensitize c to f SPECIFIC-FAULT ORIENTED TEST SET GENERATION

Fault detection and redundancy a set of inputs which detect all possible (detectable) faults is called a complete detection test set an input b = (b1… bn) distinguishes a fault  from another fault  if Z   Z  or Z   Z  = 1 a set of tests which distinguish all pairs of fault is called a complete location test set

Example : Consider fault  = x2 sa1 and  = x3 sa0 find Z 1, Z  & Z  check if (101) detects Z  check if (101) distinguishes Z  & Z  Z x1 x2 x3 Fault detection and redundancy

Z = [(x1 x2)’(x2 x3)’]’ = x1 x2 +x2 x3 = x2 (x1 + x3)  = x2 sa1 and  = x3 sa0 Z  Z  | (1,0,1) = Z  (x1+x3)=0  1 =1 Z   Z  | (1,0,1) = Z  (x1x2)= 1  0 =1 We see that the same vector x=(1,0,1) distinguishes these two faults Example : Fault detection and redundancy

If only f out of x faults have been detected by a test then “test coverage ” is t c = f/x  1 One-dimensional path sensitization A line whose value changes in the presence of the fault is sensitized to the fault by the test t. A path composed of sensitized lines is called a sensitized path. Fault detection and redundancy

x2 0 x3 0 x1 1 x4 1 Z G5 0/1 G3 G4 0/1 0 G2 0/1 G1 0 Example: consider G2 sa1 Fault detection and redundancy

Fault detection and redundancy Path sensitization algorithm I. specify inputs to generate at the site of the fault II. propagate error to the output III. specify inputs to obtain signal values needed in II IC circuit modification from: http://www.wintech-nano.com/services_ic

c i AND 0 0 OR 1 0 NAND 0 1 NOR 1 1 c x x c  i x c x c  i x x c c  i c’ c’ c’ c’  i Truth tables requires 2 n entries Input Scanning is simpler gates described by Element evaluation - c -- controlling value - i -- inversion

all inputs of G sensitized to f have the same value (say a) all not sensitized inputs have value c’ the output of Gate is equal a  i Lemma: Gate with c, i - controlling and inversion values Fault detection and redundancy c i AND 0 0 OR 1 0 NAND 0 1 NOR 1 1 c x x c  i x c x c  i x x c c  i c’ c’ c’ c’  i

The rules for error propagation with sensitized inputs equal to a Fault detection and redundancy c i Gate Other inputs Output 0 0AND all must be 1 a 0 1NAND all must be 1 a’ 1 0 OR all must be 0 a 1 1 NOR all must be 0 a’

Example : Diagnose sa0 fault at G 2 G 8 =D x 1 =0 x 3 =0 x 2 =0 x 3 =0 x 2 =0 x 4 =0 x 2 =0 G 4 =0 G 5 =D’ G 6 =0 G 7 =0 x 3 =0 x 4 =1 G 1 =1 x 1 =0 G 2 =1 D G 3=1 sa0 Fault detection and redundancy Conflicting requirements

Example : Diagnose sa0 fault at G 2 G 8 =D x 1 =0 x 3 =0 x 2 =0 x 3 =0 x 2 =0 x 4 =0 x 2 =0 G 4 =0 G 5 =D’ G 6 =D’ G 7 =0 x 3 =0 x 4 =0 G 1 =1 x 1 =0 G 2 =1 D G 3=1 sa0 Fault detection and redundancy

Detectability if no test can detect fault f => f is undetectable such a circuit is redundant undetectable fault can prevent detection of another fault

Detectability Example : b sa0 is detected by t =1101 a = 0 A=1 C=0 B=1 b=1/0 0 1 0/1 1/0 1 D=1 0

Detectability Example : b sa0 is no longer detected by t =1101 if a sa1 is present a=0/1 b=1/0 0/1 1/0 0 0/1 1/0 1 D=1 0 A=1 C=0 B=1

Detectability Undetectable fault simplification rule AND (NAND) input sa1 remove input AND (NAND) input sa0 remove gate, replace by 0(1) OR (NOR) input sa0 remove input OR (NOR) input sa1remove gate, replace by 1(0) Redundant circuit can always be simplified by removing a gate or gate input Rules

Detectability Triple modular redundancy (TMR) is used in fault tolerant design. TMR is untestable, off line testing possible for individual modules only A M A A

F= ab + a’c = 1u1 Redundancy may be used to avoid hazards Example : Consider : b=c=1, a changes from 1 to 0 a=1u0 b=111 c=111 Y X=1u0 Z=0u1 redundant Detectability

Copyright(c)2001, Samiha Mourad30 Boolean Algebra Boolean function F(x) maps domain B n to B, where B = {1,0} and F: B n  B. For any element c  B, the constant function is f(x i )= c, where x i  B n For any x i  B n, the projection function is f(x i )= x i The set of variables {x 1, x 2,  x n } is called the cube or support of the function A Boolean function can be expressed in different forms, for instance

Boolean difference Definition : The Boolean difference of f(x) is equal D(f) = df(x)/dx = f(x)  f(x’) An equivalent definition results from the following Shannon’s law f(x) = x f(1) + x’ f(0) Lemma: f(x)  f(x’) = f(0)  f(1) Then the Boolean difference is

Boolean difference Boolean difference of a product is simple df(x 1 x 2 …x n )/dx 1 =0  x 2 …x n = x 2 …x n And a Boolean difference of a sum is df(x 1 +x 2 +…+x n )/dx 1 = (x 2 +…+x n )  1= = (x 2 +…+x n )’=x’ 2 …x’ n

Boolean difference x sa0 will be tested by input vectors that satisfy : T 0 = x (df/dx) =1 x sa1 will be tested by T 1 = x’(df/dx) =1 Theorem: Boolean difference can be used to obtain all tests for stuck-at faults

Copyright(c)2001, Samiha Mourad34 Fault Detection Consider an example function f (x) = g (x) +x 3,where g(x) = x 1 x 2, Thus df (x)/dx 2 = x 3  (x 1 + x 3 ) = x 3 ’x 1 = 1. then x 1 = 1 and x 3 = 0. For the SA1 and SA0 faults on x 2, the test patterns are then x 1 x 2 x 3 = (100) and (110), respectively.

Copyright(c)2001, Samiha Mourad35 Fault Detection: Repeat calculations for stuck-at faults on x3. df (x)/dx 3 = g (x)  1 = x 1 x 2  1 = (x 1 x 2 )'. Test patterns to detect all the faults x 3 /0 and x 3 /1 are T 0 =x 3 (x 1 x 2 )' = 1 and T 1 =x 3 ’ (x 1 x 2 )' = 1. for x 3 /0, we must have x 3 x' 1 +x 3 x' 2 = 1, this results in three test patterns: x 1 x 2 x 3 = (001, 011, or 101) and for x 3 /1, we have x 1 x 2 x 3 = (000, 010, or 100)

Boolean difference G5 f x2 x3 x1 x4 G1 G2 G3 G4 Example : Find set of tests for x 1 sa1 in the circuit

Boolean difference Example : T 1 = x 1 ’(df/dx 1 ) = x 1 ’{f(0)  f(1)} = x 1 ’ [x 4  (x 2 + x 3 )] = x 1 ’(x 4 x 2 ’x 3 ’ + x 4 ’x 2 + x 4 ’x 3 ) x=0001 is a solution which sensitize the path x 1 G 2 G 4 G 5 G5 f x2 x3 x1 x4 G1 G2 G3 G4

Boolean difference Transistor level circuit modification on 90nm process from http://www.wintech-nano.com/services_ic

Boolean difference f x1x2x1x2 Example : find the Boolean difference of f w.r.t. x2

Boolean difference Example : Not testable

Boolean difference Theorem : The set of all tests which detect h sa0 is defined by : And h sa1 is defined by :

To Propagate Fault, Set x = 1, y or z =0 For c/1, must set c = 0, So v = w = 1 Test for c/1 v w x y z 1 1 1 0 1 1 1 1 1 0 1 1 1 0 0 TEST PATTERN GENERATION – BOOLEAN DIFFERENCE a v w x y z c d e g h j f 1 b x(yz)’

Boolean difference Example : Find all h sa0 tests f x1x2x1x2 x3x4x3x4 h

Boolean difference Example : Find all h sa0 tests f x1x2x1x2 x3x4x3x4 h

Boolean difference Example : Find G 1 sa1 tests G5 f x2 x3 x1 x4 G1 G2 G3 G4

Boolean difference Example : Find G 1 sa1 tests G5 f x2 x3 x1 x4 G1 G2 G3 G4

Boolean difference Boolean difference can be formed by concatenating Boolean differences (Simple chain rule)

Boolean difference Lemma : (Hong Dai)

Boolean difference Test for multiple faults

Boolean difference Test for multiple faults

Copyright(c)2001, Samiha Mourad52 Finite State Machine A finite state machine is formally expressed as a 6-tuplet (I, S, , S 0, O, ), where  I is the finite non-empty set of inputs  S is the finite and non-empty set of states  : S x I  S is the next state function  S 0  S is the set of initial states  O is the set of outputs  : S x I  O is the output function for a Mealy machine,  : S  O is the output function for a Moore machine.

Copyright(c)2001, Samiha Mourad53 Graphical & Tabular Representation Table 3.3 State Table for FSM M IPSNSOut 0AC1 1AB0 PresentNext State0BC0 StateI=0I=11BB1 AC,1B,00CD1 BC,0B,11CC1 CD,1C,10DA1 DA,1C,01DC0 Q Q SET CLR D Combinational Circuit I Z z Clk Graphical Representation (FSM)

Copyright(c)2001, Samiha Mourad54 Binary Decision Diagram ( a ) x 1 x 2 x 1 x 2 10 1 1 0 0 x 1 + x 2 x 1 x 2 1 0 1 1 0 0 ( b ) f =

Copyright(c)2001, Samiha Mourad55 Binary Decision Diagram x 2 x 4 + x 2 'x 3 x 3 x 1 x 2 1 1 0 0 x 4 x 3 x 3 x 1 1 0 0 1 1 1 1 0 0 0 0 1 x 1 x 2 x 3 x 4 f g (a) (c) (b) f =x 1 x 2 x 4 + x 1 `x 3 + x 2 `x 3

Wikipedia56 Binary Decision Diagram Binary decision tree and truth table for the function f(x1, x2, x3) = x1’ x2 ‘x3’ + x1 x2 + x2 x3 BDD for the function f

Copyright(c)2001, Samiha Mourad57 Test Generation with BDD f=g+x 3 =x 1 x 2 + x 3  To get the Boolean difference for x 1 we need to find paths to x 1 =1 and x 1 =0 from1 and 0 function values using the same internal signals (no fork at any node) so df/d x 1 =x 2 x 3 ’  The same procedure for internal signal g df/dg=x 3 ’ g 1 1 0 0 0 1 x 1 x 2 x 3 f 0 1 (b) 1 1 0 0 0 1 x 1 x 2 x 3 f 0 1 (a)

Copyright(c)2001, Samiha Mourad58 0 1 1 1 1 0 0 0 0 1 x 1 x 2 x 3 x 4 f Test Generation with BDD For Boolean function f =x 1 x 2 x 4 + x 1 ‘x 3 + x 2 ‘x 3 Boolean difference to test for x 1 s_a faults is df/d x 1 = x 2 x 4 x 3 ’ + x 2 x 4 ’x 3

Copyright(c)2001, Samiha Mourad59 Conclusion Design Representation Models used in Fault Simulation Path Sensitization to Detect a Fault Boolean Difference Complete Detection and Location Sets Finite State Machines Binary Decision Diagrams

Download ppt "2015-4-13 Based on text by S. Mourad "Priciples of Electronic Systems" Digital Testing: Design Representation and Fault Detection"

Similar presentations