1. 8/28/2015 Based on text by S. Mourad "Priciples of Electronic Systems" and M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits Digital Testing: Role of Simulation in Testing

2. Outline Verification and Simulation Verification Types of Simulation Fault Simulation Parallel Simulation Concurrent Simulation Deductive Simulation Fault Coverage Fault Dictionary

3. Types of simulation Event is a change in signal value Useful for accurate timing models Useful for asynchronous circuits Compiled simulator (table-driven) Functional verification Activity directed (event-driven)simulator

4. Types of Simulators Logic versus Fault Compiled versus event driven Functional versus timing Logic versus other levels (RTL or switch) Mixed level Emulators

5. Simulation of Large Systems Explosion in number of gates used Not possible with software to complete Move to simulation of the whole circuit on RTL level e.g. use of testbench in HDL Cycle based Simulation simulation of components at different levels using different simulator relate the results using the same clock

6. Simulation System

7. Testbench: Example in Verilog ' timescale 1ns/1ns// Time unit is 1ns module adder;// Design Testbench reg PA, PB, PCI; wire PCO,PSUM; FA_Behav F1(PA, PB, PCI, PSUM,PCO); // Instantiate module under test initial begin: ONLY_ONCE reg[3:0] Count;// Count hold the count of stimuli //4 bits are needed to accommodate up to 8. for (Count=0; Count < 8; PAL =Count +1) begin {PA, PB, PCI} =Count;//The stimuli are the values of Count #5 $display ("PA, PB, PCI=%b%b%b", PA, PB, PCI,":::PCO, PSUM=%b%b", PCO, PSUM); //Creation of the response display end endmodule

8. Logic Simulation Verifies both function & timing Check that operation is : independent on initial state not sensitive to variations in delays free of races, oscillations, illegal & hung-up states

9. Logic Simulation Software Based Slow Hardware Accelerators Simulation algorithm is hardwired Improves performance with large set of inputs Emulator Prototyping and real time simulation e.g. using FPGAs to implement the design Pentium was emulated on 3500 Xilinx3000 FGPAs EPROM Emulator

10. Logic Simulation Levels Circuit description Programming language-like HDL Connectivity of Boolean gates, flip-flops and transistors Transistor size and connectivity, node capacitances Transistor technology data, connectivity, node capacitances Tech. Data, active/ passive component connectivity Signal values 0, 1 0, 1, X and Z 0, 1 and X Analog voltage Analog voltage, current Timing Clock boundary Zero-delay unit-delay, multiple- delay Zero-delay Fine-grain timing Continuous time Modeling level Function, behavior, RTL Logic Switch Timing Circuit Application Architectural and functional verification Logic verification and test Logic verification Timing verification Digital timing and analog circuit verification

11. 0 1 X 0 0  0 1  1 1 X 0 1 X A cube of the Boolean function is a vector A simplified truth table based on singular cubes is called a singular cover Rules for intersection of cubes in Boolean logic Singular cover

12. Exercise Check if the following cubes describe a logic function C11 1 x0 C20 1 01 C30 x 11 C40 0 x0

13. Exercise Check if the following cubes describe a logic function C11 1 x0 C20 1 01 C30 x 11 C40 0 x0 No, since 001 would cause 2 different output values as it belongs to both c3 and c4

14. Unknown logic value Initial state of powered-up FF & RAMs is unpredictable u -- denotes unknown logic value (0 or 1) Boolean operation with u is a union of all operations on different values like OR(0,u)=OR{{0},{0,1}}={OR(0,0),OR(0,1)}={1,0}=u 0 1 X U 0 0  0  1  1 1  X 0 1 X U U   U U Intersection of cubes in 3 valued logic

16. u 1 u 0 u u u Pessimistic result in 3-valued simulation Since not(u) = u

17. Determine value of the logic function defined by the following cubes a)X100 b)11X0 c)X0X1 d)0 1 11 For the input vector I=(10u) using simulation Exercise

18. True-Value Simulation Algorithms Compiled-code simulation Applicable to zero-delay combinational logic Also used for cycle-accurate synchronous sequential circuits for logic verification Efficient for highly active circuits, but inefficient for low- activity circuits High-level (e.g., C language) models can be used Event-driven simulation Only gates or modules with input events are evaluated (event means a signal change) Delays can be accurately simulated for timing verification Efficient for low-activity circuits Can be extended for fault simulation

19. Compiled-Code Algorithm Step 1: Levelize combinational logic and encode in a programming language Step 2: Initialize internal state variables (flip- flops) Step 3: For each input vector Set primary input variables Repeat (until steady-state or max. iterations) Execute compiled code Report or save computed variables

20. Levelization for Compiled Simulation

22. Event-driven simulation flow Advance simulation time Propagate events Schedule resulting events Evaluate activated elements Update values Determine current events done No more events

23. Delay models (a) Nominal transition-independent transport delay (b) Rise and fall delays (c) Ambiguous delay (d) Inertial delay (pulse suppression) (e) Output inertial delay

24. ACCCCCACCCCC 3 2 3 1 5 3 R1R2 1 (a) d=2 (b) dr=1, df=3 (c) dm=1, dM=3 (d) dI = 4, (e) dI=2, d=3 A B=1 C Delay models (a)Nominal transition-independent transport delay (b) Rise and fall delays (c) Ambiguous delay (d) Inertial delay (minimum duration of input pulse) (e) Output inertial delay 3

25. Output inertial delay ABAB C dI = 3 ABCABC 2 3 2 The gate cannot produce impulse shorter than dI

26. ABCABC 2 2 1 3 3 Output inertial delay dI = 3 ABAB C

27. d1 d2 Wire delays modeled by delay elements

28. c x x c  i x c x c  i x x c c  i c’ c’ c’ c’  i c i AND 0 0 OR 1 0 NAND 0 1 NOR 1 1 Truth tables quires 2 n entries Input Scanning gates described by - c -- controlling value - i -- inversion Element evaluation

29. Evaluate (G, c, i) begin u_values = FALSE for every input value v of G begin if v = c then return c  i if v = u then u_values = TRUE end if u_values return u return c’  i end Gate evaluation in 3-valued logic by scanning input values

30. evaluate (G, c, i) begin if c_count > 0 then return c  i if u_count > 0 then return u return c’  i end Advantage: No need to store the multiple input values (only two counters for c_count and u_count are updated during simulation) For instance in AND gate 1->0 change on its input increases c_count while 0->u transition increases u_count and decreases c_count. Gate evaluation in 3-valued logic based on input counting

31. Hazard Detection R Q S ABAB Z (Static hazard) ABZABZ Latch may be reset

32. Unknown signal value B t t’ t+1 ==> B(t)B(t’)B(t+1) = 0u1 Also : A(t)A(t’)A(t+1) = 1u0 Z = (AB)’ = 1u1  {101, 111} - possible static hazard

33. Static Hazard Detection Denote by E the set of inputs changing between t and t+1 Procedure 3.1 1.Set every input E to u and simulate to get output Z(t’) 2.Set every input E to its value at t+1 and simulate to get Z(t+1) Theorem 3.1 In a combinational circuit, a static hazard exists iff Z(t)Z(t’)Z(t+1) is 1u1 or 0u0

34. Hazard Detection (a) 0 delay : B = 101, C = 000 (b) unit delay : B = 1101, C = 0100 (c) arbitrary delay : A = 0u1u0, B = 1u0u1 => C = 0u0u0 (hazard) C A B If A = 010 then: Check the following circuit for static hazards

35. 6-valued logic for static hazard analysis ValueSequence(s)Meaning 0000Static 0 1111Static 1 0/1, R{001, 011} = 0u1Rise (0 to 1) transition 1/0, F{110, 100} = 1u0Fall (1 to 0) transition 0*{000, 010} = 0u0Static 0-hazard 1*{111, 101} = 1u1Static 1-hazard

36. AND truth table for 6-valued logic

37. Dynamic Hazards Dynamic hazards occur during transition 1->0 or 0->1 So they require 4 bit sequences to detect 1010 or 0101  To detect them in simulation 8 valued logic is used.  8 valued logic can detect both static and dynamic hazards

38. 8-valued logic

39. Exercise To determine result of Boolean operation in 8 valued logic all possible sequences must be used For instance to calculate AND(R,1 * ) we have AND(R,1 * )=AND({0x11,00x1},{1ux1,1xu1})= {0uu1,00u1}=R * Rules for inversion NOT(F)=R,NOT(0*)=1*,NOT(F*)=R*

40. NAND truth table for 8-valued logic Exercise:Calculate NAND(R,R * )

41. NAND truth table for 8-valued logic Exercise:Calculate NAND(R,R * ) NAND(R,R * ) = NAND({0x11,00x1},{0u01,01u1}) = NOT({0u01,01u1,0001,00u1}) = {1u10,10u0,1110,11u0}=F * Exercise: Calculate NAND(F,R * )

42. Event-Driven Procedure Event-Driven-Simulator: Read circuit description Read input vectors FOR each input vector to be simulated DO Process new inputs Update input nodes Schedule connected elements on timing wheel WHILE elements left for evaluation Evaluate element IF change on the output THEN update all fanouts and schedule Connect element on timing wheel END WHILE END FOR End procedure

43. Gate level event-driven simulation Only the activated gates are analyzed. Not all entries in the event list are events ABAB Z ABZABZ 0 2 4 6 8 10 12 8 10 12 (Z, 1) (Z, 0) (Z, 0) Not an event

44. Event Simulation While (event list not empty) begin t = next time in list process entries for time t end There is no events on G3, G5, G7, G8, and G9 due to F=1

45. Time Wheel (Circular Stack) t=0 1 2 3 4 5 6 7 max Current time pointer Event link-list

46. The Time Wheel Time in ns is computed modulo M  = t c mod M for events t c  t e  t c + M-1 If t c + M  t e then the event is put on the overflow queue 1   t c M i, v i ’j, v j ’ *

47. Event-Driven Algorithm (Example) 2 2 4 2 a =1 b =1 c =1 0 d = 0 e =1 f =0 g =1 Time, t 0 4 8 g t = 0 1 2 3 4 5 6 7 8 Scheduled events c = 0 d = 1, e = 0 g = 0 f = 1 g = 1 Activity list d, e f, g g Time stack

48. Timing Simulation (a) G AND1 AND2 OR1 INV A B C D=1 C' E F Delay  Unit delay Variable delay Rise and fall delay

49. Static Timing Simulation Critical path delay Using the circuit and worst case analysis of delays low complexity Problems No consideration for the function False path

50. Oscillation Control Local oscillation can be controlled by setting unstable feedback signals to u Global oscillations are hard to control -- they are avoided by limiting the simulation time. When oscillation occur during simulation they waste simulator efforts – the same loops are traversed again and again

51. Other logic values Tristate logic -- several devices share a bus. Each driving device is controlled by the enable signal E. Simulator should report potential conflicts when a bus is driven by 0 and 1 01Zu 00ucuc 0u 1ucuc 11u Z01Zu uuuuu

52. Other logic values MOS logic -- Transmission gates act like bus driver, except when the gate is open the wire connected to its output retains its previous value. u 0 1 ZuZu Z0Z0 Z1Z1 Z Relative strength of logic values used in MOS Simulation. Weak values are caused by open circuits

53. Logic Strength Signals A and B may be undetermined if S=1 depending on the drivers strength

54. Exercise for MOS simulation A I B E D H G C F Use inputs from the following table to find signals C,F,H,I A B D E G 1 1 0 1 0 1 0 0 1 1 0 1 1 0 1 1 0 1 0 0

55. Exercise for MOS simulation A I B E D H G C F Use inputs from the following table to find signals C,F,H,I A B D E G 1 1 0 1 0 1 0 0 1 1 0 1 1 0 1 1 0 1 0 0 C F H I 0 1 Z 0 |1 1 0 0 1 Z 1 |1 0 0 Z 1 Z 1 0 0