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Computer ArchitectureFall 2008 © August 20 th, 2008 www.qatar.cmu.edu Introduction to Computer Architecture Lecture 2 – Digital Logic Design.

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Presentation on theme: "Computer ArchitectureFall 2008 © August 20 th, 2008 www.qatar.cmu.edu Introduction to Computer Architecture Lecture 2 – Digital Logic Design."— Presentation transcript:

1 Computer ArchitectureFall 2008 © August 20 th, 2008 www.qatar.cmu.edu Introduction to Computer Architecture Lecture 2 – Digital Logic Design

2 Computer ArchitectureFall 2008 © Digital Systems Digital vs. Analog Waveforms Analog: values vary over a range continuously Digital: only assumes discrete values +5 V –5 Time

3 Computer ArchitectureFall 2008 © Digital Hardware Systems Algebra: variables, values, operations In Boolean algebra, the values are the symbols 0 and 1 If a logic statement is false, it has value 0 If a logic statement is true, it has value 1 Operations: AND, OR, NOT Boolean Algebra and Logical Operators

4 Computer ArchitectureFall 2008 © L1 L6L6 L2 L3 L7L7 L4L4 L5L5 Example: Seven Segment Display °Chip to drive digital display

5 Computer ArchitectureFall 2008 © L1 L6L6 L2 L3 L7L7 L4L4 L5L5 Example (cont.)

6 Computer ArchitectureFall 2008 © Example (cont.) °Implement L4: Some gate level implementation of the Boolean function for L4

7 Computer ArchitectureFall 2008 © Representations of Digital Design: Switches A switch connects two points under control signal. when the control signal is 0 (false), the switch is open when it is 1 (true), the switch is closed when control is 1 (true), switch is open when control is 0 (false), switch is closed Normally Closed Normally Open

8 Computer ArchitectureFall 2008 © Switch Representations Examples: routing inputs to outputs through a maze Floating nodes: what happens if the car is not running? outputs are floating rather than forced to be false Under all possible control signal settings (1) all outputs must be connected to some input through a path (2) no output is connected to more than one input through any path

9 Computer ArchitectureFall 2008 © Steering Logic: Switches Voltage Controlled Switches Metal Gate, Oxide, Silicon Sandwich Diffusion regions: negatively charged ions driven into Si surface Si Bulk: positively charged ions By "pulling" electrons to the surface, a conducting channel is formed "n-Channel MOS" n-type Si p-type Si

10 Computer ArchitectureFall 2008 © Switching or Steering Logic Voltage Controlled Switches Logic 0 on gate, Source and Drain connected Logic 1 on gate, Source and Drain connected

11 Computer ArchitectureFall 2008 © Using Switches to implement Logic Inverter Operation +5V "1" "0" +5V "0" "1" Input is 1 Pull-up does not conduct Pull-down conducts Output connected to GND Input is 0 Pull-up conducts Pull-down does not conduct Output connected to VDD

12 Computer ArchitectureFall 2008 © NAND Gate NAND Gate Operation A = 1, B = 1 Pull-up network does not conduct Pull-down network conducts Output node connected to GND A = 0, B = 1 Pull-up network has path to VDD Pull-down network path broken Output node connected to VDD +5V "1" "0" +5V "0" "1"

13 Computer ArchitectureFall 2008 © NOR Gate NOR Gate Operation +5V "0" "1" +5V "1" "0" A = 0, B = 0 Pull-up network conducts Pull-down network broken Output node at VDD A = 1, B = 0 Pull-up network broken Pull-down network conducts Output node at GND

14 Computer ArchitectureFall 2008 © Switch Representations Implementation of AND and OR Functions with Switches AND function Series connection to TRUE OR function Parallel connection to TRUE

15 Computer ArchitectureFall 2008 © Representations of a Digital Design Truth Tables tabulate all possible input combinations and their associated output values Example: half adder adds two binary digits to form Sum and Carry Example: full adder adds two binary digits and Carry in to form Sum and Carry Out NOTE: 1 plus 1 is 0 with a carry of 1 in binary

16 Computer ArchitectureFall 2008 © Representing Digital Design: Boolean Algebra NOT X is written as X X AND Y is written as X & Y, or sometimes X Y X OR Y is written as X + Y values: 0, 1 variables: A, B, C,..., X, Y, Z operations: NOT, AND, OR,... A0011A0011 B0101B0101 Sum 0 1 0 Carry 0 1 Sum = A B + A B Carry = A B OR'd together product terms for each truth table row where the function is 1 if input variable is 0, it appears in complemented form; if 1, it appears uncomplemented Deriving Boolean equations from truth tables:

17 Computer ArchitectureFall 2008 © Representing Digital Logic: Boolean Algebra A00001111A00001111 B00110011B00110011 Cin 0 1 0 1 0 1 0 1 Sum 0 1 1 0 1 0 0 1 Cout 0 0 0 1 0 1 1 1 Another example: Sum = A B Cin + A B Cin + A B Cin + A B Cin Cout = A B Cin + A B Cin + A B Cin + A B Cin

18 Computer ArchitectureFall 2008 © Gate Representations of a Digital Design most widely used primitive building block in digital system design Standard Logic Gate Representation Half Adder Schematic Netlist: tabulation of gate inputs & outputs and the nets they are connected to Net: electrically connected collection of wires A B CARRY SUM

19 Computer ArchitectureFall 2008 © Representations of a Digital Design: Gates Full Adder Schematic Fan-in: number of inputs to a gate Fan-out: number of gate inputs an output is connected to Technology "Rules of Composition" place limits on fan-in/fan-out

20 Computer ArchitectureFall 2008 © Waveform Representation dynamic behavior of a circuit real circuits have non-zero delays Timing Diagram of the Half Adder sum propagation delay circuit hazard: 1 plus 0 is 1, not 0! sum propagation delay Output changes are delayed from input changes The propagation delay is sensitive to paths in the circuit Outputs may temporarily change from the correct value to the wrong value back again to the correct value: this is called a glitch or hazard

21 Computer ArchitectureFall 2008 © Routing Stuff Around – Multiplexors and Demultiplexors Multi-point connections MUX DEMUX A B Sum A0A1B0 B1 SaSb Ss S0S1 Multiple input sources Multiple output destinations

22 Computer ArchitectureFall 2008 © So far Combinatorial (or stateless) logic °Things don’t get really interesting until we have memory elements Think about a digital watch, or a vending machine (or a microprocessor!) This is called “Sequential Logic” °Two questions: How do we design memory elements? -How do we create logic that remembers? How do we design sequential logic

23 Computer ArchitectureFall 2008 © Memory Elements °The trick is to use feedback Cascaded Inverters: Static Memory Cell "0" "1" °Example: D-Latch °Latch vs. Flip Flop Flip flop: two latches in a row Allows you to read the old value and write a new value without a race condition DQ D Clk Q

24 Computer ArchitectureFall 2008 © Sequential Logic Design °State as part of the input °Next state as part of the output °State stored in flip flops (registers!) °Clock controls everything (synchronous logic) °Lets rethink our 8 segment display example to make it display a counter inputs outputs Combinatorial Logic State Current state Next state

25 Computer ArchitectureFall 2008 © Take home points °Logic built using switches (transistors) °Boolean algebra and truth tables °Translation to gates: sum of products °Multiplexors, demultiplexors, ALU … all designed this way °Sequential logic Memory elements Old state part of inputs, next state part of outputs Counters, registers, control all designed this way

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