1. 05/12/06BR Fall 991 Programmable Logic So far, have only talked about PALs (see 22V10 figure next page). What is the next step in the evolution of PLDs? –More gates! How do we get more gates? We could put several PALs on one chip and put an interconnection matrix between them!! –This is called a Complex PLD (CPLD).

2. 05/12/06BR Fall 992 22V10 PLD

3. 05/12/06BR Fall 993 Cypress CPLD Each logic block is similar to a 22V10. Programmable interconnect matrix.

4. 05/12/06BR Fall 994 Any other approaches? Another approach to building a “better” PLD is place a lot of primitive gates on a die, and then place programmable interconnect between them:

5. 05/12/06BR Fall 995 Field Programmable Gate Arrays The FPGA approach to arrange primitive logic elements (logic cells) arrange in rows/columns with programmable routing between them. What constitutes a primitive logic element? Lots of different choices can be made! Primitive element must be classified as a “complete logic family”. A primitive gate like a NAND gate A 2/1 mux (this happens to be a complete logic family) A Lookup table (I.e, 16x1 lookup table can implement any 4 input logic function). Often combine one of the above with a DFF to form the primitive logic element.

6. 05/12/06BR Fall 996 Other FPGA features Besides primitive logic elements and programmable routing, some FPGA families add other features Embedded memory –Many hardware applications need memory for data storage. Many FPGAs include blocks of RAM for this purpose Dedicated logic for carry generation, or other arithmetic functions Phase locked loops for clock synchronization, division, multiplication.

7. 05/12/06BR Fall 997 Altera Flex 10K FPGA Family

8. 05/12/06BR Fall 998 Altera Flex 10K FPGA Family (cont)

9. 05/12/06BR Fall 999 Dedicated memory

10. 05/12/06BR Fall 9910 16 x1 LUT DFF

11. 05/12/06BR Fall 9911

12. 05/12/06BR Fall 9912 Emedded Array Block Memory block, Can be configured: –256 x 8, 512 x 4, 1024 x 2, 2048 x 1

13. 05/12/06BR Fall 9913 Issues in FPGA Technologies Complexity of Logic Element –How many inputs/outputs for the logic element? –Does the basic logic element contain a FF? What type? Interconnect –How fast is it? Does it offer ‘high speed’ paths that cross the chip? How many of these? –Can I have on-chip tri-state busses? –How routable is the design? If 95% of the logic elements are used, can I route the design? More routing means more routability, but less room for logic elements

14. 05/12/06BR Fall 9914 Issues in FPGA Technologies (cont) Macro elements –Are there SRAM blocks? Is the SRAM dual ported? –Is there fast adder support (i.e. fast carry chains?) –Is there fast logic support (i.e. cascade chains) –What other types of macro blocks are available (fast decoders? register files? ) Clock support –How many global clocks can I have? –Are there any on-chip Phase Logic Loops (PLLs) or Delay Locked Loops (DLLs) for clock synchronization, clock multiplication?

15. 05/12/06BR Fall 9915 Issues in FPGA Technologies (cont) What type of IO support do I have? –TTL, CMOS are a given –Support for mixed 5V, 3.3v IOs? 3.3 v internal, but 5V tolerant inputs? –Support for new low voltage signaling standards? GTL+, GTL (Gunning Tranceiver Logic) - used on Pentium II HSTL - High Speed Transceiver Logic SSTL - Stub Series-Terminate Logic USB - IO used for Universal Serial Bus (differential signaling) AGP - IO used for Advanced Graphics Port –Maximum number of IO? Package types? Ball Grid Array (BGA) for high density IO

16. 05/12/06BR Fall 9916 Altera FPGA Family Summaries Altera Flex10K/10KE –LEs (Logic elements) have 4-input LUTS (look-up tables) +1 FF –Fast Carry Chain between LE’s, Cascade chain for logic operations –Large blocks of SRAM available as well Altera Max7000/Max7000A –EEPROM based, very fast (Tpd = 7.5 ns) –Basically a PLD architecture with programmable interconnect. –Max 7000A family is 3.3 v

17. 05/12/06BR Fall 9917 Xilinx FPGA Family Summaries Virtex Family –SRAM Based –Largest device has 1M gates –Configurable Logic Blocks (CLBs) have two 4-input LUTS, 2 DFFs –Four onboard Delay Locked Loops (DLLs) for clock synchronization –Dedicated RAM blocks (LUTs can also function as RAM). –Fast Carry Logic XC4000 Family –Previous version of Virtex –No DLLs, No dedicated RAM blocks

18. 05/12/06BR Fall 9918 Actel FPGA Family Summaries MXDS Family –Fine grain Logic Elements that contain Mux logic + DFF –Embedded Dual Port SRAM –One Time Programmable (OTP) - means that no configuration loading on powerup, no external serial ROM –AntiFuse technology for programming (AntiFuse means that you program the fuse to make the connection). –Fast (Tpd = 7.5 ns) –Low density compared to Altera, Xilinx - maximum number of gates is 36,000

19. 05/12/06BR Fall 9919 Cypress CPLDs Ultra37000 Family –32 to 512 Macrocells –Fast (Tpd 5 to 10ns depending on number of macrocells) –Very good routing resources for a CPLD

20. BR Fall 9920 trend toward higher levels of integration Evolution of Implementation Technologies Discrete devices: relays, transistors (1940s-50s) Discrete logic gates (1950s-60s) Integrated circuits (1960s-70s) e.g. TTL packages: Data Book for 100’s of different parts Map your circuit to the Data Book parts Gate Arrays (IBM 1970s) “Custom” integrated circuit chips Design using a library (like TTL) Transistors are already on the chip Place and route software puts the chip together automatically + Large circuits on a chip + Automatic design tools (no tedious custom layout)  - Only good if you want 1000’s of parts

21. BR Fall 9921 Gate Array Technology (IBM - 1970s)  Simple logic gates  Use transistors to implement combinational and sequential logic  Interconnect  Wires to connect inputs and outputs to logic blocks  I/O blocks  Special blocks at periphery for external connections  Add wires to make connections  Done when chip is fabbed  “mask-programmable”  Construct any circuit

22. BR Fall 9922 Programmable Logic  Disadvantages of the Data Book method  Constrained to parts in the Data Book  Parts are necessarily small and standard  Need to stock many different parts  Programmable logic  Use a single chip (or a small number of chips)  Program it for the circuit you want  No reason for the circuit to be small

23. BR Fall 9923 Programmable Logic Technologies  Fuse and anti-fuse  Fuse makes or breaks link between two wires  Typical connections are 50-300 ohm  One-time programmable (testing before programming?)  Very high density  EPROM and EEPROM  High power consumption  Typical connections are 2K-4K ohm  Fairly high density  RAM-based  Memory bit controls a switch that connects/disconnects two wires  Typical connections are.5K-1K ohm  Can be programmed and re-programmed in the circuit  Low density

24. BR Fall 9924 Programmable Logic  Program a connection  Connect two wires  Set a bit to 0 or 1  Regular structures for two-level logic (1960s-70s)  All rely on two-level logic minimization  PROM connections - permanent  EPROM connections - erase with UV light  EEPROM connections - erase electrically  PROMs  Program connections in the _____________ plane  PLAs  Program the connections in the ____________ plane  PALs  Program the connections in the ____________ plane

25. BR Fall 9925 Making Large Programmable Logic Circuits  Alternative 1 : “CPLD”  Put a lot of PLDS on a chip  Add wires between them whose connections can be programmed  Use fuse/EEPROM technology  Alternative 2: “FPGA”  Emulate gate array technology  Hence Field Programmable Gate Array  You need:  A way to implement logic gates  A way to connect them together

26. BR Fall 9926 Field-Programmable Gate Arrays  PALs, PLAs = 10 - 100 Gate Equivalents  Field Programmable Gate Arrays = FPGAs  Altera MAX Family  Actel Programmable Gate Array  Xilinx Logical Cell Array  100 - 1000(s) of Gate Equivalents!

27. BR Fall 9927 Field-Programmable Gate Arrays  Logic blocks  To implement combinational and sequential logic  Interconnect  Wires to connect inputs and outputs to logic blocks  I/O blocks  Special logic blocks at periphery of device for external connections  Key questions:  How to make logic blocks programmable?  How to connect the wires?  After the chip has been fabbed

28. BR Fall 9928 Tradeoffs in FPGAs  Logic block - how are functions implemented: fixed functions (manipulate inputs) or programmable?  Support complex functions, need fewer blocks, but they are bigger so less of them on chip  Support simple functions, need more blocks, but they are smaller so more of them on chip  Interconnect  How are logic blocks arranged?  How many wires will be needed between them?  Are wires evenly distributed across chip?  Programmability slows wires down – are some wires specialized to long distances?  How many inputs/outputs must be routed to/from each logic block?  What utilization are we willing to accept? 50%? 20%? 90%?

29. BR Fall 9929 8 Product Term AND-OR Array + Programmable MUX's Programmable polarity I/O Pin Seq. Logic Block Programmable feedback Altera EPLD (Erasable Programmable Logic Devices)  Historical Perspective  PALs: same technology as programmed once bipolar PROM  EPLDs: CMOS erasable programmable ROM (EPROM) erased by UV light  Altera building block = MACROCELL

30. BR Fall 9930 Altera EPLDs contain 8 to 48 independently programmed macrocells Personalized by EPROM bits: Flipflop controlled by global clock signal local signal computes output enable Flipflop controlled by locally generated clock signal + Seq Logic: could be D, T positive or negative edge triggered + product term to implement clear function Altera EPLD

31. BR Fall 9931 AND-OR structures are relatively limited Cannot share signals/product terms among macrocells Logic Array Blocks (similar to macrocells) Global Routing: Programmable Interconnect Array 8 Fixed Inputs 52 I/O Pins 8 LABs 16 Macrocells/LAB 32 Expanders/LAB EPM5128: Altera Multiple Array Matrix (MAX)

32. BR Fall 9932 LAB Architecture Expander Terms shared among all macrocells within the LAB

33. BR Fall 9933 Supports large number of product terms per output Latches and muxes associated with output pins P22V10 PAL

34. BR Fall 9934 Rows of programmable logic building blocks + rows of interconnect Anti-fuse Technology: Program Once 8 input, single output combinational logic blocks FFs constructed from discrete cross coupled gates Use Anti-fuses to build up long wiring runs from short segments Actel Programmable Gate Arrays

35. BR Fall 9935 Basic Module is a Modified 4:1 Multiplexer Example: Implementation of S-R Latch Actel Logic Module

36. BR Fall 9936 Interconnection Fabric Actel Interconnect

37. BR Fall 9937 Jogs cross an anti-fuse minimize the # of jobs for speed critical circuits 2 - 3 hops for most interconnections Actel Routing Example

38. BR Fall 9938 Xilinx Programmable Gate Arrays  CLB - Configurable Logic Block  5-input, 1 output function  or 2 4-input, 1 output functions  optional register on outputs  Built-in fast carry logic  Can be used as memory  Three types of routing  direct  general-purpose  long lines of various lengths  RAM-programmable  can be reconfigured

39. BR Fall 9939 Programmable Interconnect I/O Blocks (IOBs) Configurable Logic Blocks (CLBs)

40. BR Fall 9940 The Xilinx 4000 CLB

41. BR Fall 9941 Two 4-input functions, registered output

42. BR Fall 9942 5-input function, combinational output

43. BR Fall 9943 CLB Used as RAM

44. BR Fall 9944 Fast Carry Logic

45. BR Fall 9945 Xilinx 4000 Interconnect

46. BR Fall 9946 Switch Matrix

47. BR Fall 9947 Xilinx 4000 Interconnect Details

48. BR Fall 9948 Global Signals - Clock, Reset, Control

49. BR Fall 9949 Xilinx 4000 IOB

50. BR Fall 9950 Xilinx FPGA Combinational Logic Examples  Key: General functions are limited to 5 inputs  (4 even better - 1/2 CLB)  No limitation on function complexity  Example  2-bit comparator: A B = C D and A B > C D implemented with 1 CLB (GT)F = A C' + A B D' + B C' D' (EQ)G = A'B'C'D'+ A'B C'D + A B'C D'+ A B C D  Can implement some functions of > 5 input

51. BR Fall 9951 CLB 5-input Majority Circuit CLB 7-input Majority Circuit Xilinx FPGA Combinational Logic  Examples  N-input majority function: 1 whenever n/2 or more inputs are 1  N-input parity functions: 5 input/1 CLB; 2 levels yield 25 inputs! CLB 9 Input Parity Logic

52. BR Fall 9952 Xilinx FPGA Adder Example  Example  2-bit binary adder - inputs: A1, A0, B1, B0, CIN outputs: S0, S1, Cout Full Adder, 4 CLB delays to final carry out 2 x Two-bit Adders (3 CLBs each) yields 2 CLBs to final carry out

53. BR Fall 9953 Computer-Aided Design  Can't design FPGAs by hand  Way too much logic to manage, hard to make changes  Hardware description languages  Specify functionality of logic at a high level  Validation: high-level simulation to catch specification errors  Verify pin-outs and connections to other system components  Low-level to verify mapping and check performance  Logic synthesis  Process of compiling HDL program into logic gates and flip- flops  Technology mapping  Map the logic onto elements available in the implementation technology (LUTs for Xilinx FPGAs)

54. BR Fall 9954 CAD Tool Path (cont’d)  Placement and routing  Assign logic blocks to functions  Make wiring connections  Timing analysis - verify paths  Determine delays as routed  Look at critical paths and ways to improve  Partitioning and constraining  If design does not fit or is unroutable as placed split into multiple chips  If design it too slow prioritize critical paths, fix placement of cells, etc.  Few tools to help with these tasks exist today  Generate programming files - bits to be loaded into chip for configuration

55. BR Fall 9955 Xilinx CAD Tools  Verilog (or VHDL) use to specify logic at a high-level  Combine with schematics, library components  Synopsys  Compiles Verilog to logic  Maps logic to the FPGA cells  Optimizes logic  Xilinx APR - automatic place and route (simulated annealing)  Provides controllability through constraints  Handles global signals  Xilinx Xdelay - measure delay properties of mapping and aid in iteration  Xilinx XACT - design editor to view final mapping results

56. BR Fall 9956 Applications of FPGAs  Implementation of random logic  Easier changes at system-level (one device is modified)  Can eliminate need for full-custom chips  Prototyping  Ensemble of gate arrays used to emulate a circuit to be manufactured  Get more/better/faster debugging done than with simulation  Reconfigurable hardware  One hardware block used to implement more than one function  Functions must be mutually-exclusive in time  Can greatly reduce cost while enhancing flexibility  RAM-based only option  Special-purpose computation engines  Hardware dedicated to solving one problem (or class of problems)  Accelerators attached to general-purpose computers