1. Temporizzazioni e sincronismo1 Progettazione di circuiti e sistemi VLSI Anno Accademico 2010-2011 Lezione 10 3.5.2011 Temporizzazioni e sincronizzazione

2. Temporizzazioni e sincronismo2 Synchronous Timing t c-q t p,comb t c-q,cd t cdlog t su, t hold

3. Temporizzazioni e sincronismo3 Latch Parameters D Clk Q D Q t c-q t hold PW m t su t d-q Delays can be different for rising and falling data transitions T t c-q + t p,comb + t su ≤ T t c-q,cd + t cdlog > t hold

4. Temporizzazioni e sincronismo4 Register Parameters D Clk Q D Q t c-q t hold T t su Delays can be different for rising and falling data transitions

5. Temporizzazioni e sincronismo5 Clock Uncertainties Sources of clock uncertainty

6. Temporizzazioni e sincronismo6 Clock Nonidealities Clock skew –Spatial variation in temporally equivalent clock edges; deterministic + random, t SK Clock jitter –Temporal variations in consecutive edges of the clock signal; modulation + random noise –Cycle-to-cycle (short-term) t JS –Long term t JL Variation of the pulse width –Important for level sensitive clocking

7. Temporizzazioni e sincronismo7 Clock Skew and Jitter Both skew and jitter affect the effective cycle time Only skew affects the race margin Clk t SK t JS

8. Temporizzazioni e sincronismo8 Clock Skew # of registers Clk delay Insertion delay Max Clk skew Earliest occurrence of Clk edge Nominal –  /2 Latest occurrence of Clk edge Nominal +  /2 

9. Temporizzazioni e sincronismo9 Positive and Negative Skew

10. Temporizzazioni e sincronismo10 Positive Skew Launching edge arrives before the receiving edge

11. Temporizzazioni e sincronismo11 Negative Skew Receiving edge arrives before the launching edge

12. Temporizzazioni e sincronismo12 Timing Constraints Minimum cycle time: T -  = t c-q + t su + t logic Worst case is when receiving edge arrives early (positive  negative skew)

13. Temporizzazioni e sincronismo13 Timing Constraints Hold time constraint: t (c-q, cd) + t (logic, cd) > t hold +  Worst case is when receiving edge arrives late Race between data and clock

14. Temporizzazioni e sincronismo14 Impact of Jitter

15. Temporizzazioni e sincronismo15 Longest Logic Path in Edge-Triggered Systems Clk T t SU t Clk-Q T LM Latest point of launching Earliest arrival of next cycle t JI + 

16. Temporizzazioni e sincronismo16 Clock Constraints in Edge-Triggered Systems If launching edge is late and receiving edge is early, the data will not be too late if: Minimum cycle time is determined by the maximum delays through the logic t c-q + T Lm,cd + t SU < T – t JI,1 – t JI,2 -  t c-q + T Lm,cd + t SU +  + 2 t JI < T Skew can be either positive or negative

17. Temporizzazioni e sincronismo17 Shortest Path Clk t Clk-Q T Lm,cd Earliest point of launching Data must not arrive before this time Clk tHtH Nominal clock edge

18. Temporizzazioni e sincronismo18 Clock Constraints in Edge-Triggered Systems Minimum logic delay If launching edge is early and receiving edge is late: t c-q,cd + T Lm,cd – t JI,1 < t H + t JI,2 +  t c-q,cd + T Lm,cd < t H + 2t JI + 

19. Temporizzazioni e sincronismo19 How to counter Clock Skew?

20. Temporizzazioni e sincronismo20 Latch-Based Design L1 Latch Logic L2 Latch  L1 latch is transparent when  = 0 L2 latch is transparent when  = 1

21. Temporizzazioni e sincronismo21 Clock Distribution Clock is distributed in a tree-like fashion H-tree

22. Temporizzazioni e sincronismo22 The Grid System No rc-matching Large power

23. Temporizzazioni e sincronismo23 Self-timed and Asynchronous Design Functions of clock in synchronous design 1) Acts as completion signal 2) Ensures the correct ordering of events Truly asynchronous design 2) Ordering of events is implicit in logic 1) Completion is ensured by careful timing analysis Self-timed design 1) Completion ensured by completion signal 2) Ordering imposed by handshaking protocol

24. Temporizzazioni e sincronismo24 Synchronous Pipelined Datapath