1. A/D Converter Datapaths Discussion D8.4

2. Analog-to-Digital Converters Converts analog signals to digital signals –8-bit: 0 – 255 –10-bit: 0 – 1023 –12-bit: 0 – 4095 Successive Approximation

3. Method of Successive Approximation

4. Implementing Successive Approximation

6. A/D CPLD

7. A/D CPLD Datapath

8. A/D Datapath 1000 0100 0010 0001 0000 mask SAR B 1000 1100 1110 1111 0000 1000 1100 1110 1111

9. module maskReg(clk,reset,sh,Q); input clk; input reset,sh; output [3:0] Q; reg [3:0] Q; // 4-bit Shift Register always @(posedge clk or posedge reset) begin if(reset == 1) Q <= 4'b1000; else begin if(sh == 1) begin Q[3] <= 0; Q[2:0] <= Q[3:1]; end endmodule 0000 1000 0100 0010 0001 0000 maskR

10. // Title: A/D converter datapath module ADpath(clk,reset,msel,sh,sarld,adld,sar,ADR,done); input clk,reset,msel,sh,sarld,adld; output done; output [3:0] sar,ADR; wire [3:0] sar,sarin,ADR,A,B; wire [3:0] mask; assign done = ~|mask; assign A = sar | mask; assign B = sar & ~mask; reg4 sarReg(.D(sarin),.Load(sarld),.Clear(reset),.Clk(clk),.Q(sar)); reg4 adReg(.D(sar),.Load(adld),.Clear(reset),.Clk(clk),.Q(ADR)); maskReg maskR(.clk(clk),.reset(reset),.sh(sh),.Q(mask)); mux24 mux1(.A(A),.B(B),.s(msel),.Y(sarin)); endmodule