1. How to get a Circuit in verilog converted to hspice, connected to the micron package models, and simulating in hspice and hsimplus.

2. First we need a verilog file.
// mod.v `timescale 1ns / 1ps module mod( a, out, CLK); input [3:0] a; input CLK; output [1:0] out; reg [1:0] out; CLK) begin out <= a % 3; end endmodule
These are the names of the internal inputs and outputs
This is where you declare the specs of the circuit.
The [3:0] syntax means that there are 4 wires contained in the circuit.
the output of this circuit is named out.
For us to be able to assign to out in the always block below we must also declare a reg of the same type and name.
For this circuit, the code in the always block will run every time that the CLK signal goes from low to high.

3. = vs <= operators
reg[15:0] a;
reg[15:0] b;
CLK)
begin
a=b;
b=a;
end
The = operator is verilog’s blocking assignment operator
Each statement must be evaluated and the value changed before the next.
For this circuit, a gets the value of b.
b then gets the value of a.
Result: both now contain the same value
The <= operator is verilog’s non-blocking assignment operator.
During the CLK cycle all of these updates take place simultaneously
For this circuit, a and b will switch their values at the positive edge of every CLK
reg[15:0] a; reg[15:0] b; CLK) begin a<=b; b<=a; end

4. Simulation of circuit to ensure logic correct.
Hspice and Hsimplus are not suited for simple verification of a verilog circuit.
Use Xilink or similar program to simulate the circuit and verify functionality.

5. Xilink demo
Todo (maybe) add a xilink demo (but we should aready know how to do this)
Please go on to next slide

6. Environment Setup
set path = ($path /uusoc/facility/cad_common/local/bin/S10)
set path = ($path /uusoc/facility/cad_common/local/bin/F09/)
set path = ($path /uusoc/facility/cad_common/local/bin/S09/)
set path = ($path /uusoc/facility/cad_common/local/bin/F08/)
set path = ($path /uusoc/facility/cad_common/local/bin/S08/)
set path = ($path /uusoc/facility/cad_common/local/bin/F07/)
set path = ($path /uusoc/facility/cad_common/local/bin/S07/)
set path = ($path /uusoc/facility/cad_common/local/bin/F06/)
set path = ($path /uusoc/facility/cad_common/local/bin/S06/)
set path = ($path /uusoc/facility/cad_common/local/bin/F05/)
set path = ($path /uusoc/facility/cad_common/local/bin/S05/)
set path = ($path /uusoc/facility/cad_common/local/setups/)
setenv LOCAL_CADSETUP /uusoc/facility/cad_common/local/class/6830/S09
setenv MSIM /uusoc/facility/cad_tools/Mentor/MSIM-F07
setenv FPGADV /uusoc/facility/cad_tools/Mentor/FPGADV-F07
setenv CBRE /uusoc/facility/cad_tools/Mentor/CBRE-F07
setenv FPGADV_BIN /uusoc/facility/cad_tools/Mentor/FPGADV-F07/Fpgadv/bin
setenv HDS_BIN /uusoc/facility/cad_tools/Mentor/FPGADV-F07/Hds/bin
setenv MODELTECH_BIN /uusoc/facility/cad_tools/Mentor/MSIM-F07/modeltech/bin
setenv CALIBRE_BIN /uusoc/facility/cad_tools/Mentor/CBRE-F07/bin
setenv MGC_HOME /uusoc/facility/cad_tools/Mentor/ixl_cal_2007.2_26.18/ixl_cal_2007.2_26.18/
set path = ($path /uusoc/facility/cad_tools/Mentor/FPGADV-F07/Fpgadv/bin)
set path = ($path /uusoc/facility/cad_tools/Mentor/FPGADV-F07/Hds/bin)
set path = ($path /uusoc/facility/cad_tools/Mentor/MSIM-F07/modeltech/bin)
set path = ($path /uusoc/facility/cad_tools/Mentor/CBRE-F07/bin)
setenv LM_LICENSE_FILE /uusoc/facility/cad_tools/Mentor/common_license
In order for the tools in the cade lab to work properly, you must set up the tools.
Edit your .cshrc file and include the following items

7. Conversion from Verilog to Spice
Conversion from verilog to spice is done in several step
The .v file is ran through a rtl optimization and verification script
The now optimized file is ran through the design compiler to get a structural verilog file.
The structural verilog file is converted to hspice
As an example I will be converting the mod.v file (shown earlier) to spice.

8. Step 0: Getting Ready
Run the following commands to ensure group members can read your files
newgrp micron
umask 007
Create a working directory and copy the scripts from the /home/micron/design/65nm/dc directory
namingrules.dc
Node name restriction and modification script
mult.cstr.tcl
Constraint file that defines the clock period, etc
mult.rtlopt.csh
A cshell script for launching the design compiler
mult.rtlopt.tcl
A script for generating the correct rtl optimized file
mult.dcopt.csh
A shell script for running the synthesis workflow
mult.dcopt.tcl
A script for running the full compilation
These are based off of the scripts from Ken Stevens ECE 6770 Advanced digital VLSI design class webpage
They have been modified to use the 65nm design libraries
Copy the micron package models into your new directory

9. Step 0: Getting Ready (continued)
mult.rtlopt.csh
#!/bin/csh -fb
###############################################
# This runs design compiler and creates the constraint files
# This is the first of two scripts to be run
# This one basically ensures the verilog is correct
### Script variable settings
## design compiler command - may need to run "setup-synopsys" first:
set dccmd = "syn-dc"
## design definitions
# note that csh variables do not get imported into dc_shell :-(
set design = “mult” # this should be the top level name of your design
set tool = "rtlopt“ …
Need to edit scripts so they are operating on the correct files.
Modify 4 files replacing mult with the circuit name
mult.rtlopt.tcl
### This is the script for optimizing the verilog
# #
# DESIGN DEFINITION #
set design_name mult
set design_dir ".“ …
mult.dcopt.csh
#!/bin/csh -fb
###############################################
# This runs design compiler and creates the constraint files
### Script variable settings
## design compiler command - may need to run "setup-synopsys" first:
set dccmd = "syn-dc"
## design definitions
# note that csh variables do not get imported into dc_shell :-(
set design = “mult“ # this should be the top level name of your design
set tool = "dcopt“ …
mult.dcopt.tcl
### This is the script for optimizing the verilog
# #
# DESIGN DEFINITION #
set design_name mult
set design_dir ".“ …

10. Step 0: Getting Ready (continued)
mult.cstr.csh
################################################
# tcl variable $design_name defined in calling script
current_design $design_name
# Define operational modes
set_operating_conditions "typical" -library $lib_name
set_wire_load_mode "segmented"
set_max_fanout 64 $design_name
# Define frequency parameters
set clk_period
set clk_port "CLK"
set clk_name "clock"
Adjust this value to define what clock speed we will be using
Very important to ensure that circuit is converted correctly (allows enough time for signal propagation)
We don’t know what it should be so make best guess
We will be able to check the circuit timing later and may have to come back and readjust this.
Lastly rename all of the mult.* files to {circuit_name}.*

11. Step 0: Getting Ready (continued)
mod.rtlopt.csh
#!/bin/csh -fb
###############################################
# This runs design compiler and creates the constraint files
# This is the first of two scripts to be run
# This one basically ensures the verilog is correct
### Script variable settings
## design compiler command - may need to run "setup-synopsys" first:
set dccmd = "syn-dc"
## design definitions
# note that csh variables do not get imported into dc_shell :-(
set design = “mod” # this should be the top level name of your design
set tool = "rtlopt“ …
Final state of files after step 0
mod.rtlopt.tcl
### This is the script for optimizing the verilog
# #
# DESIGN DEFINITION #
set design_name mod
set design_dir ".“ …
mod.dcopt.tcl
### This is the script for optimizing the verilog
# #
# DESIGN DEFINITION #
set design_name mod
set design_dir ".“ …
mod.cstr.csh
################################################
# tcl variable $design_name defined in calling script
current_design $design_name
# Define operational modes
set_operating_conditions "typical" -library $lib_name
set_wire_load_mode "segmented"
set_max_fanout 64 $design_name
# Define frequency parameters
set clk_period
set clk_port "CLK"
set clk_name "clock"
mod.dcopt.csh
#!/bin/csh -fb
###############################################
# This runs design compiler and creates the constraint files
### Script variable settings
## design compiler command - may need to run "setup-synopsys" first:
set dccmd = "syn-dc"
## design definitions
# note that csh variables do not get imported into dc_shell :-(
set design = “mod“ # this should be the top level name of your design
set tool = "dcopt“ …

12. Step 1: RTL Optimization and Verilog Verification
Run the rtl optimization script
./mod.rtlopt.csh
This will generate 2 files
mod.rtlopt.out
Contains a log of the conversion. Check this for errors!!
mod.rtlopt.v

13. Step 1: RTL Optimization and Verilog Verification (continued)
Result
mod.rtlopt.v is now ready for the design compiler
mod.rtlopt.v
module mod ( a, out, CLK );
input [3:0] a;
output [1:0] out;
input CLK;
wire N0, N1;
REM_UNS_OP rem_13 ( .A(a), .B({1'b1, 1'b1}), .REMAINDER({N1, N0}) );
\**SEQGEN** \out_reg[1] ( .clear(1'b0), .preset(1'b0), .next_state(N1),
.clocked_on(CLK), .data_in(1'b0), .enable(1'b0), .Q(out[1]),
.synch_clear(1'b0), .synch_preset(1'b0), .synch_toggle(1'b0),
.synch_enable(1'b1) );
\**SEQGEN** \out_reg[0] ( .clear(1'b0), .preset(1'b0), .next_state(N0),
.clocked_on(CLK), .data_in(1'b0), .enable(1'b0), .Q(out[0]),
endmodule
mod.v
`timescale 1ns / 1ps
module mod( a, out, CLK);
input [3:0] a;
input CLK;
output [1:0] out;
reg [1:0] out;
CLK)
begin
out <= a % 3;
end
Endmodule

14. Step 2: Conversion to Structural Verilog
Run the conversion script
./mod.dcopt.csh
This will generate many files
mod.dcopt.out
Contains a log of the conversion. Check this for errors!!
mod.dcopt.v
The converted structural verilog file.
mod.dcopt.fullpaths
Contains timing information from the design compiler

15. Step 2: Conversion to Structural Verilog (continued)
Result
mod.dcopt.v is now ready for conversion to hspice
mod.dcopt.v
module mod ( a, out0, CLK );
input [3:0] a;
output [1:0] out0;
input CLK;
wire n22, n23, n1, n2, n3, n5, n7, n8, n9, n10, n11, n12, n13, n14, n15,
n16, n17, n18, n19, n20, n21;
A2DFFQX1A12TR clock_r_REG2_S1 ( .A(n1), .B(n12), .CK(CLK), .Q(n10) );
DFFQX0P5A12TR clock_r_REG1_S1 ( .D(n18), .CK(CLK), .Q(n9) );
DFFQNX0P5A12TR clock_r_REG0_S1 ( .D(n15), .CK(CLK), .QN(n21) );
DFFQX0P5A12TR clock_r_REG3_S1 ( .D(n2), .CK(CLK), .Q(n8) );
OAI2XB1X1A12TR U3 ( .A1N(n8), .A0(n21), .B0(n19), .Y(n20) );
XOR2X0P7A12TR U4 ( .A(n20), .B(n8), .Y(n23) );
XNOR2X0P7A12TR U5 ( .A(n7), .B(n21), .Y(n22) );
INVX16A12TR U6 ( .A(n3), .Y(out0[0]) );
INVX16A12TR U7 ( .A(n5), .Y(out0[1]) );
BUFHX1P4A12TR U8 ( .A(a[2]), .Y(n1) );
INVX0P5BA12TR U9 ( .A(a[3]), .Y(n12) );
NAND2X0P5BA12TR U10 ( .A(a[1]), .B(n16), .Y(n18) );
BUFHX1P4A12TR U11 ( .A(a[0]), .Y(n2) );
INVX0P5BA12TR U12 ( .A(n23), .Y(n3) );
INVX0P5BA12TR U13 ( .A(n22), .Y(n5) );
OAI22X1A12TR U14 ( .A0(n17), .A1(n14), .B0(n13), .B1(n12), .Y(n16) );
INVX2A12TR U15 ( .A(a[1]), .Y(n14) );
INVX2A12TR U16 ( .A(n11), .Y(n13) );
NAND2X1A12TR U17 ( .A(a[2]), .B(n11), .Y(n17) );
XOR2X0P7A12TR U18 ( .A(n16), .B(a[1]), .Y(n15) );
NAND2X1A12TR U19 ( .A(a[3]), .B(a[2]), .Y(n11) );
AND2X1A12TR U20 ( .A(n8), .B(n20), .Y(n7) );
XOR2X0P7A12TR U21 ( .A(n9), .B(n10), .Y(n19) );
endmodule
mod.rtlopt.v
module mod ( a, out, CLK );
input [3:0] a;
output [1:0] out;
input CLK;
wire N0, N1;
REM_UNS_OP rem_13 ( .A(a), .B({1'b1, 1'b1}), .REMAINDER({N1, N0}) );
\**SEQGEN** \out_reg[1] ( .clear(1'b0), .preset(1'b0), .next_state(N1),
.clocked_on(CLK), .data_in(1'b0), .enable(1'b0), .Q(out[1]),
.synch_clear(1'b0), .synch_preset(1'b0), .synch_toggle(1'b0),
.synch_enable(1'b1) );
\**SEQGEN** \out_reg[0] ( .clear(1'b0), .preset(1'b0), .next_state(N0),
.clocked_on(CLK), .data_in(1'b0), .enable(1'b0), .Q(out[0]),
endmodule

16. Step 2: Conversion to Structural Verilog (continued)
Excerpt from mod.dcopt.fullpaths
Startpoint: a[2] (input port)
Endpoint: clock_r_REG0_S1
(rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: max
Point Incr Path
clock (input port clock) (rise edge)
input external delay r
a[2] (in) r
U19/Y (NAND2X1A12TR) f
U17/Y (NAND2X1A12TR) r
U14/Y (OAI22X1A12TR) f
U18/Y (XOR2X0P7A12TR) f
clock_r_REG0_S1/D (DFFQNX0P5A12TR) f
data arrival time
clock clock (rise edge)
clock network delay (ideal)
clock uncertainty
clock_r_REG0_S1/CK (DFFQNX0P5A12TR) r
library setup time
data required time
data arrival time
slack (MET)
Timing verification
Look though the fullpaths file to ensure that there is no negative slack
If there is any negative slack or too much positive slack edit the clock speed in the mod.cstr.tcl and rerun steps 1 and 2

17. Step 3: Conversion to Spice
Run the v2lvs conversion program
v2lvs -v {INPUT FILE} -o {OUTPUT FILE} -lsr {LIBRARY FILE} –i
v2lvs -v mod.dcopt.v -o mod.v2lvs.sp -lsr /home/micron/design/65nm/data/cmos10sfrvt_A12.cdl –I
Where is power and ground
They are there, but we need to run one more script so we can see them.
mod.v2lvs.sp
$ Spice netlist generated by v2lvs
$ v2007.2_ Wed Jun 13 20:11:48 PDT 2007
.SUBCKT mod a[3] a[2] a[1] a[0] out0[1] out0[0] CLK
Xclock_r_REG2_S1 n10 n1 n12 CLK A2DFFQX1A12TR
Xclock_r_REG1_S1 n9 CLK n DFFQX0P5A12TR
Xclock_r_REG0_S1 n21 CLK n DFFQNX0P5A12TR
Xclock_r_REG3_S1 n8 CLK n DFFQX0P5A12TR
XU3 n20 n21 n8 n OAI2XB1X1A12TR
XU4 n23 n20 n XOR2X0P7A12TR
XU5 n22 n7 n XNOR2X0P7A12TR
XU6 out0[0] n INVX16A12TR
XU7 out0[1] n INVX16A12TR
XU8 n1 a[2] BUFHX1P4A12TR
XU9 n12 a[3] INVX0P5BA12TR
XU10 n18 a[1] n NAND2X0P5BA12TR
XU11 n2 a[0] BUFHX1P4A12TR
XU12 n3 n INVX0P5BA12TR
XU13 n5 n INVX0P5BA12TR
XU14 n16 n17 n14 n13 n OAI22X1A12TR
XU15 n14 a[1] INVX2A12TR
XU16 n13 n INVX2A12TR
XU17 n17 a[2] n NAND2X1A12TR
XU18 n15 n16 a[1] XOR2X0P7A12TR
XU19 n11 a[3] a[2] NAND2X1A12TR
XU20 n7 n8 n AND2X1A12TR
XU21 n19 n9 n XOR2X0P7A12TR
.ENDS

18. Step 3: Conversion to Spice (continued)
Use the emacs script v2lvs-convert.el to convert the spice file and add power and grounds
Open the v2lvs-convert.el file in emacs
emacs v2lvs-convert.el
Press escape and then ‘x’
Type in ‘eval-current-buffer’ and press enter
Press ctrl-x and then ctrl-f to open a new file
Type in the filename (mod.v2lvs.sp) and press enter
Type in ‘convert-v2lvs’ and press enter
Press ctrl-x and then ctrl-s to save the file
Press ctrl-x and then ctrl-c to exit emacs

19. Step 3: Conversion to Spice
Result
Our circuit now has VSS and VDD references to the internal parts.
Need to make one more change.
The mod circuit does not define VSS or VDD as being accessible from an outside circuit.
Add ‘ VDD VSS’ to the line starting with .SUBCKT to make those ports accessible.
mod.v2lvs.sp (with VDD,VSS addition)
$ Spice netlist generated by v2lvs
$ v2007.2_ Wed Jun 13 20:11:48 PDT 2007
.SUBCKT mod a[3] a[2] a[1] a[0] out0[1] out0[0] CLK VDD VSS
Xclock_r_REG2_S1 n10 n1 n12 CLK VDD VSS A2DFFQX1A12TR
Xclock_r_REG1_S1 n9 CLK n18 VDD VSS DFFQX0P5A12TR
Xclock_r_REG0_S1 n21 CLK n15 VDD VSS DFFQNX0P5A12TR
Xclock_r_REG3_S1 n8 CLK n2 VDD VSS DFFQX0P5A12TR
XU3 n20 n21 n8 n19 VDD VSS OAI2XB1X1A12TR
XU4 n23 n20 n8 VDD VSS XOR2X0P7A12TR
XU5 n22 n7 n21 VDD VSS XNOR2X0P7A12TR
XU6 out0[0] n3 VDD VSS INVX16A12TR
XU7 out0[1] n5 VDD VSS INVX16A12TR
XU8 n1 a[2] VDD VSS BUFHX1P4A12TR
XU9 n12 a[3] VDD VSS INVX0P5BA12TR
XU10 n18 a[1] n16 VDD VSS NAND2X0P5BA12TR
XU11 n2 a[0] VDD VSS BUFHX1P4A12TR
XU12 n3 n23 VDD VSS INVX0P5BA12TR
XU13 n5 n22 VDD VSS INVX0P5BA12TR
XU14 n16 n17 n14 n13 n12 VDD VSS OAI22X1A12TR
XU15 n14 a[1] VDD VSS INVX2A12TR
XU16 n13 n11 VDD VSS INVX2A12TR
XU17 n17 a[2] n11 VDD VSS NAND2X1A12TR
XU18 n15 n16 a[1] VDD VSS XOR2X0P7A12TR
XU19 n11 a[3] a[2] VDD VSS NAND2X1A12TR
XU20 n7 n8 n20 VDD VSS AND2X1A12TR
XU21 n19 n9 n10 VDD VSS XOR2X0P7A12TR
.ENDS
mod.v2lvs.sp
$ Spice netlist generated by v2lvs
$ v2007.2_ Wed Jun 13 20:11:48 PDT 2007
.SUBCKT mod a[3] a[2] a[1] a[0] out0[1] out0[0] CLK
Xclock_r_REG2_S1 n10 n1 n12 CLK A2DFFQX1A12TR
Xclock_r_REG1_S1 n9 CLK n DFFQX0P5A12TR
Xclock_r_REG0_S1 n21 CLK n DFFQNX0P5A12TR
Xclock_r_REG3_S1 n8 CLK n DFFQX0P5A12TR
XU3 n20 n21 n8 n OAI2XB1X1A12TR
XU4 n23 n20 n XOR2X0P7A12TR
XU5 n22 n7 n XNOR2X0P7A12TR
XU6 out0[0] n INVX16A12TR
XU7 out0[1] n INVX16A12TR
XU8 n1 a[2] BUFHX1P4A12TR
XU9 n12 a[3] INVX0P5BA12TR
XU10 n18 a[1] n NAND2X0P5BA12TR
XU11 n2 a[0] BUFHX1P4A12TR
XU12 n3 n INVX0P5BA12TR
XU13 n5 n INVX0P5BA12TR
XU14 n16 n17 n14 n13 n OAI22X1A12TR
XU15 n14 a[1] INVX2A12TR
XU16 n13 n INVX2A12TR
XU17 n17 a[2] n NAND2X1A12TR
XU18 n15 n16 a[1] XOR2X0P7A12TR
XU19 n11 a[3] a[2] NAND2X1A12TR
XU20 n7 n8 n AND2X1A12TR
XU21 n19 n9 n XOR2X0P7A12TR
.ENDS
mod.v2lvs.sp (after emacs)
$ Spice netlist generated by v2lvs
$ v2007.2_ Wed Jun 13 20:11:48 PDT 2007
.SUBCKT mod a[3] a[2] a[1] a[0] out0[1] out0[0] CLK
Xclock_r_REG2_S1 n10 n1 n12 CLK VDD VSS A2DFFQX1A12TR
Xclock_r_REG1_S1 n9 CLK n18 VDD VSS DFFQX0P5A12TR
Xclock_r_REG0_S1 n21 CLK n15 VDD VSS DFFQNX0P5A12TR
Xclock_r_REG3_S1 n8 CLK n2 VDD VSS DFFQX0P5A12TR
XU3 n20 n21 n8 n19 VDD VSS OAI2XB1X1A12TR
XU4 n23 n20 n8 VDD VSS XOR2X0P7A12TR
XU5 n22 n7 n21 VDD VSS XNOR2X0P7A12TR
XU6 out0[0] n3 VDD VSS INVX16A12TR
XU7 out0[1] n5 VDD VSS INVX16A12TR
XU8 n1 a[2] VDD VSS BUFHX1P4A12TR
XU9 n12 a[3] VDD VSS INVX0P5BA12TR
XU10 n18 a[1] n16 VDD VSS NAND2X0P5BA12TR
XU11 n2 a[0] VDD VSS BUFHX1P4A12TR
XU12 n3 n23 VDD VSS INVX0P5BA12TR
XU13 n5 n22 VDD VSS INVX0P5BA12TR
XU14 n16 n17 n14 n13 n12 VDD VSS OAI22X1A12TR
XU15 n14 a[1] VDD VSS INVX2A12TR
XU16 n13 n11 VDD VSS INVX2A12TR
XU17 n17 a[2] n11 VDD VSS NAND2X1A12TR
XU18 n15 n16 a[1] VDD VSS XOR2X0P7A12TR
XU19 n11 a[3] a[2] VDD VSS NAND2X1A12TR
XU20 n7 n8 n20 VDD VSS AND2X1A12TR
XU21 n19 n9 n10 VDD VSS XOR2X0P7A12TR
.ENDS

20. Spice File Simulation
We now have the a spice file of our verilog circuit
Now we need a control file for simulation
Simpler to do it without the micron package models at first
Hard to program from scratch without example

21. Control Files .include and .lib tell the simulator what files to use.
mod.wop.sp
SPICE simulation of our simple inverter
* SPICE simulation of our simple inverter
* include our circuit
.include 'mod.v2lvs.sp'
* include the library
.include '/home/micron/design/65nm/data/cmos10sfrvt_a12.cdl'
* include the transistor models
.lib '/home/micron/design/65nm/data/skew.file' stats
.include '/home/micron/design/65nm/data/fixed_corner'
.include '/home/micron/design/65nm/data/hspice_example.param'
.lib '/home/micron/design/65nm/data/lib.models.10sf' 10sf_models
**.include '/home/micron/design/65nm/data/nfet.inc'
**.include '/home/micron/design/65nm/data/pfet.inc'
*** define usage of the subcircuits
x1 DIE_DQ3 DIE_DQ2 DIE_DQ1 DIE_DQ0 DIE_DQ5 DIE_DQ4 DIE_DQ6 pwr1 gnd mod
* ".option post" generates the outputs for cscope
.option acct=1 post
*Give initial Voltage and ground powers
.nodeset v(pwr1) = 1.2 v(gnd) = 0.0
*Give Initial signal voltages
.nodeset v(DIE_DQ0) = 1.2 v(DIE_DQ2) = 1.2 v(DIE_DQ4) = 1.2
+ v(DIE_DQ6) = 1.2
* set up our power and ground sources
VCC1 pwr1 0 DC 1.2
VSS1 gnd 0 DC 0.0
(continued on next slide)
.include and .lib tell the simulator what files to use.
We include our mod.v2lvs.sp which contains our circuit
Instantiates and defines use of sub-circuits (more on this later)
Makes the simulator generate waveform outputs
Defines initial voltages (helps hsimplus and hspice)
Defines the voltage and ground pins

22. Control Files (continued)
mod.wop.sp (continued)
* define input waves for first gate.
* these are switching simultaneously.
* PULSE commands are initial-voltage pulse-voltage, time-offset,
* rise-time fall-time high-delay cycle-time
VA3 DIE_DQ3 0 PULSE( p 100p 100p 10000p 20000p)
VA2 DIE_DQ2 0 PULSE( p 100p 100p 10000p 20000p)
VA1 DIE_DQ1 0 PULSE( p 100p 100p 10000p 20000p)
VA0 DIE_DQ0 0 PULSE( p 100p 100p 10000p 20000p)
VA6 DIE_DQ6 0 PULSE( p 100p 100p 1000p 2000p)
.save type=nodeset level=all
*** This lowers precision - 1 is default (up to 4)
.param hsimparprecision = 0
* run a transitent analysis for two clock cycles
.TRAN 1p 40000p START=0ps
* plot transient voltages
.PLOT TRAN V(DIE_DQ0) V(0) (0,1.2)
.PLOT TRAN V(DIE_DQ1) V(0) (0,1.2)
.PLOT TRAN V(DIE_DQ2) V(0) (0,1.2)
.PLOT TRAN V(DIE_DQ3) V(0) (0,1.2)
.PLOT TRAN V(DIE_DQ4) V(0) (0,1.2)
.PLOT TRAN V(DIE_DQ5) V(0) (0,1.2)
.PLOT TRAN V(DIE_DQ6) V(0) (0,1.2)
.PLOT TRAN V(pwr1) V(0) (0,1.2)
.PLOT TRAN V(gnd) V(0) (0,1.2)
* measure the power
.MEAS rmsen rms I(VCC) from = 0ps to 40000ps
.end
Define inputs for the circuits
Here we are doing a 10000ps pulse with various offsets for DIE_DQ0-DIE_DQ3
DIE_DQ6 here is a clock signal
Sets hsim’s precision factor. (lower is slower)
Instructs the simulator to simulate for a specific amount of time. (40000 pico-seconds)
Instructs the simulator to plot the output waveforms of signals from 0 to 1.2 volts
Measures the average (rms) power of VCC from 0ps to 40000ps

23. Control Files (continued)
*** define usage of the subcircuits
x1 DIE_DQ3 DIE_DQ2 DIE_DQ1 DIE_DQ0 DIE_DQ5 DIE_DQ4 DIE_DQ6 pwr1 gnd mod
Where do we get all of this info
x# at the start gives it a unique identifier for this instantiation of this circuit
mod at the end tells us what circuit it is
The rest of them are arbitrary names chosen by whatever naming scheme you see fit.
So what should I put here and how many of them should I put?
First look at the spice file
.SUBCKT mod a[3] a[2] a[1] a[0] out0[1] out0[0] CLK VDD VSS
x1 DIE_DQ3 DIE_DQ2 DIE_DQ1 DIE_DQ0 DIE_DQ5 DIE_DQ4 DIE_DQ6 pwr1 gnd mod
Remember these names have been arbitrary chosen

24. Control Files (continued)
To connect circuits
Set the name of the outputs of one to be the inputs of another
In this example the outputs of mod circuit x1 used as some of the inputs to x2
x1 DIE_DQ3 DIE_DQ2 DIE_DQ1 DIE_DQ0 DIE_DQ5 DIE_DQ4 DIE_DQ6 pwr1 gnd mod
x2 DIE_DQ7 DIE_DQ8 DIE_DQ5 DIE_DQ4 DIE_DQ9 DIE_DQ10 DIE_DQ6 pwr1 gnd mod

25. Control Files (continued)
The same principals apply to using the micron control files
Only much more complicated
Use example code

26. Micron Single Layer Model
Add the following to the control file
*** include the single layer package
.include 'v48c_x8_production_11704_DQs_pkg.inc'
***using the single layer power delivery package
x0 DIE_DQ0_PKG001 DIE_DQ1_PKG001 DIE_DQ2_PKG001 DIE_DQ3_PKG001
+ DIE_DQ4_PKG001 DIE_DQ5_PKG001 DIE_DQ6_PKG001 DIE_DQ7_PKG001 DIE_DQS_PKG001
+ DIE_DQS#_PKG001 DIE_DM_PKG001 DIE_TDQS#_PKG001 gnd gnd gnd gnd gnd gnd
+ gnd gnd gnd gnd gnd gnd pwrQ pwrQ pwrQ1 pwrQ2 pwrQ3 pwrQ3 pwrQ3 gnd gnd
+ gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd pwr pwr pwr1 pwr2 pwr3 pwr
+ pwr pwr pwr pwr pwr pwr pwr BGA_VSSA_PKG001 BGA_VSSB_PKG001 BGA_VSSC_PKG001
+ BGA_VSSD_PKG001 BGA_VSSE_PKG001 BGA_VSSF_PKG001 BGA_VCCA_PKG001
+ BGA_VCCB_PKG001 BGA_VCCC_PKG001 BGA_VCCD_PKG001 BGA_VSSQ1_PKG001
+ BGA_VSSQ2_PKG001 BGA_VSSQ3_PKG001 BGA_VSSQ4_PKG001 BGA_VSSQ_PKG001
+ BGA_VCCQ2_PKG001 BGA_VCCQ3_PKG001 BGA_VCCQ_PKG001 BGA_VCCQ1_PKG001
+ BGA_VSS1_PKG001 BGA_VSS2_PKG001 BGA_VSS3_PKG001 BGA_VSS4_PKG001
+ BGA_VSS_PKG001 BGA_VCC3_PKG001 BGA_VCC_PKG001 BGA_VCC1_PKG001
+ BGA_VCC2_PKG001 BGA_TDQS#_PKG001 BGA_DM_PKG001 BGA_DQS#_PKG001
+ BGA_DQS_PKG001 BGA_DQ7_PKG001 BGA_DQ6_PKG001 BGA_DQ5_PKG001 BGA_DQ4_PKG001
+ BGA_DQ3_PKG001 BGA_DQ2_PKG001 BGA_DQ1_PKG001 BGA_DQ0_PKG001
+ v48c dq-str-pwrs-unmer_wrapper

27. Micron 2 Layer Model Add the following to the control file
*** include the 2 layer package
.include 'v48c_x8_2metal_layer_0523_DQs_pkg.inc'
***using the 2 layer power delivery package
x0 DIE_DQ0_PKG001 DIE_DQ1_PKG001 DIE_DQ2_PKG001 DIE_DQ3_PKG001
+ DIE_DQ4_PKG001 DIE_DQ5_PKG001 DIE_DQ6_PKG001 DIE_DQ7_PKG001 DIE_DQS_PKG001
+ DIE_DQS#_PKG001 DIE_DM_PKG001 DIE_TDQS#_PKG001 gnd gnd gnd gnd gnd gnd gnd
+ gnd gnd gnd gnd gnd pwrQ1 pwrQ1 pwrQ pwrQ pwrQ pwrQ pwrQ1 gnd gnd gnd gnd
+ gnd gnd gnd gnd gnd gnd gnd gnd gnd pwr pwr pwr pwr pwr pwr pwr1 pwr pwr
+ pwr pwr pwr pwr BGA_VSSQ1A_PKG001 BGA_VSSQ1B_PKG001 BGA_VSSQC_PKG001
+ BGA_VCCQ_PKG001 BGA_VCCQ1_PKG001 BGA_VSSA_PKG001 BGA_VSSB_PKG001
+ BGA_VSSC_PKG001 BGA_VSSD_PKG001 BGA_VSSE_PKG001 BGA_VSSF_PKG001
+ BGA_VSSG_PKG001 BGA_VSSH_PKG001 BGA_VSSI_PKG001 BGA_VCCA_PKG001
+ BGA_VCCB_PKG001 BGA_VCCC_PKG001 BGA_VCCD_PKG001 BGA_VCCE_PKG001
+ BGA_VCCF_PKG001 BGA_VSSQ1_PKG001 BGA_VSSQ_PKG001 BGA_VCCQ3_PKG001
+ BGA_VCCQ2_PKG001 BGA_VSS1_PKG001 BGA_VSS_PKG001 BGA_VCC1_PKG001
+ BGA_VCC_PKG001 BGA_TDQS#_PKG001 BGA_DM_PKG001 BGA_DQS#_PKG001
+ BGA_DQS_PKG001 BGA_DQ7_PKG001 BGA_DQ6_PKG001 BGA_DQ5_PKG001
+ BGA_DQ4_PKG001 BGA_DQ3_PKG001 BGA_DQ2_PKG001 BGA_DQ1_PKG001 BGA_DQ0_PKG001
+ sol_v48c_523_dq_dm_str_pwr_unmergedSnks_wrapper

28. Connecting Circuits to Packages
To connect the mod circuit to the package we use the following format
Give mod’s inputs the same name as the DIE side inputs of the package
DIE_DQ#_PCG001
BGA_DQ#_PKG001
MOD
Input Stimulus (CLK,RESET,etc)

29. Connecting Circuits to Packages (continued)
To connect the two mod circuits internally in a single package we use the following format
Give mod’s inputs the same name as the DIE side inputs of the package and /or inputs from the other mod circuit
DIE_DQ#_PCG001
BGA_DQ#_PKG001
MOD x1
Input Stimulus (CLK,RESET,etc)
MOD x2

30. Connecting Circuits to Packages (continued)
To connect the 2 mod circuits that are in different packages we do the following
Give mod’s inputs the same name as the DIE side inputs of the package
DIE_DQ#_PCG001
BGA_DQ#_PKG001
MOD x1
DIE_DQ#_PCG002
BGA_DQ#_PKG002
MOD x2
Input Stimulus (CLK,RESET,etc)

31. Simulation in Hspice and Hsimplus
The commands to simulate have similar formats
hspice -i mod.singlelayer.control -o mod.singlelayer.hspice.out
syn-hsimplus –I mod.singlelayer.control -o mod.singlelayer.hsimplus.out
These commands may take a while. (especially hspice)
When finished we should be able to open the results and view waveforms in c-scope
Command is syn-cscope
Modelsim output files are of in the .fsdb format

32. C-Scope output