1. CSE 201 Computer Logic Design * * * * * * * Verilog Modeling
Basics
CSULB -- CECS 201– Verilog Basics
© R.W. Allison

2. EDA Design Tool Suites — e.g. Xilinx, Altera, ModelSim
Electronic Design & Automation (EDA) Tools
EDA Design Tool Suites — e.g. Xilinx, Altera, ModelSim
Schematics
Table Data
Hardware Definition
Languages (HDL’s)
Core Generators
State Diagrams
Verilog
VHDL
Structural
Dataflow
Behavioral
Instances of other modules (objects) are interconnected with wires. Outputs are type “wire”
Assign statements for implementation of combination logic. Outputs are type “wire”
Always blocks using the event operator using higher level logic decision statements. Outputs are type “reg”
CSULB -- CECS 201– Verilog Basics
© R.W. Allison

3. Two Primary Ways of Modeling Logic
Behavioral
Structural
Use “always” block
DO NOT use “always”
Outputs declared as “reg”
Outputs declared as “wire”
“Schematics using text”
“Instantiate” other modules
(e.g. gates, 1-bit adders, etc.) and interconnect them with
wires and busses.
Combinational Logic
Sequential Logic
(*)
(posedge clk, posedge reset)
case ( {all inputs} )
if ( reset == 1’b1 ) // check for reset first
// assign output(s) for reset condition
// each row assigns output(s)
// based on input combinations
else // got a clock
// assign output(s) based on decisions
CSULB -- CECS 201– Verilog Basics
© R.W. Allison

4. Fundamentals Verilog Module Definitions
Module name (must begin with a letter or underscore)
Port list (input and output names)
module addsub ( M, A, B, Cin, Y, CB );
input [3:0] A, B;
input M, Cin;
output [3:0] Y;
output CB;
input/output declarations
reg [3:0] Y;
reg CB;
output type declarations
size specifier (default size is 1-bit scalar)
event operator
sensitivity list
always @ ( M, A, B, Cin ) begin
// behavioral logic of add/sub
if ( M == 1’b0 )
{CB,Y} = A + B + Cin;
else
{CB,Y} = A - B - Cin;
single line comment
Note: Verilog is an “event driven” language,
not a “sequential” language.
concatenation operator
As such, the most powerful operator in the
verilog language is the “event” operator
end // end of always
endmodule
In practical use, the second most powerful
operator is the concatenation operator ( { , } ).
CSULB -- CECS 201– Verilog Basics
© R.W. Allison