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CSULB -- CECS 201– Verilog Basics © 2015 -- R.W. Allison 1.

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Presentation on theme: "CSULB -- CECS 201– Verilog Basics © 2015 -- R.W. Allison 1."— Presentation transcript:

1 CSULB -- CECS 201– Verilog Basics © R.W. Allison 1

2 2 EDA Design Tool Suites — e.g. Xilinx, Altera, ModelSim Schematics State Diagrams Instances of other modules (objects) are interconnected with wires. Outputs are type “wire” CSULB -- CECS 201– Verilog Basics © R.W. Allison Table Data Hardware Definition Languages (HDL’s) Core Generators Verilog VHDL Structural Behavioral Dataflow Assign statements for implementation of combination logic. Outputs are type “wire” Always blocks using the event operator using higher level logic decision statements. Outputs are type “reg”

3 3 Behavioral Structural Use “always” block DO NOT use “always” Outputs declared as “reg” Outputs declared as “wire” Combinational Logic Sequential Logic (*) (posedge clk, posedge reset) case ( {all inputs} ) if ( reset == 1’b1 ) // check for reset first // assign output(s) for reset condition // each row assigns output(s) // based on input combinations else // got a clock // assign output(s) based on decisions “Instantiate” other modules (e.g. gates, 1-bit adders, etc.) and interconnect them with wires and busses. “Schematics using text” CSULB -- CECS 201– Verilog Basics © R.W. Allison

4 4 module addsub ( M, A, B, Cin, Y, CB ); Module name (must begin with a letter or underscore) Port list (input and output names) input [3:0] A, B; input M, Cin; output [3:0] Y; output CB; input/output declarations size specifier (default size is 1-bit scalar) reg[3:0] Y; reg CB; output type declarations ( M, A, B, Cin ) begin event operator sensitivity list // behavioral logic of add/sub if ( M == 1’b0 ) {CB,Y} = A + B + Cin; else {CB,Y} = A - B - Cin; end // end of always single line comment endmodule concatenation operator Note: Verilog is an “event driven” language, not a “sequential” language. As such, the most powerful operator in the verilog language is the “event” operator In practical use, the second most powerful operator is the concatenation operator ( {, } ). CSULB -- CECS 201– Verilog Basics © R.W. Allison


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