Recall Divide-by-8 Counter Use Q2, Q1, Q0 as inputs to a combinational circuit to produce an arbitrary waveform. s s s s s s s s State Q2 Q1 Q0 D2 D1 D0 Present state Next state Q0 Q1 Q2 D0 D1 D2
s s s s s s s s State Q2 Q1 Q0 D2 D1 D0 y Example Q2 Q1 Q y = ~Q2 & ~Q1 | Q2 & Q
Counters Divide-by-8 Counter Behavioral Counter in Verilog Counter using One-Hot State Machine
One-Hot State Machines Instead of using the minimum number of flip-flops (3) to implement the state machine, one-hot encoding uses one flip-flop per state (8) to implement the state machine. Q0 Q1 Q2 D0 D1 D2
Why use One-Hot State Machines? Using one-hot encoding or one flip-flop per state (8) will normally simplify the combinational logic at the expense of more flip-flops. Let's see how for the 3-bit counter
One-Hot Encoding s s1 s s2 s s3 s s4 s s5 s s6 s s7 s s0 State Q2 Q1 Q0 D[0:7] Present state Next state Think of each state as a flip-flop D[i] = s[i-1] This is just a ring counter!
s s s s s s s s State Q2 Q1 Q0 Q2 = s4 | s5 | s6 | s7 Q1 = s2 | s3 | s6 | s7 Q0 = s1 | s3 | s5 | s7 3-bit Counter