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Counters Discussion D8.3. Counters Divide-by-8 Counter Behavioral Counter in Verilog Counter using One-Hot State Machine.

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Presentation on theme: "Counters Discussion D8.3. Counters Divide-by-8 Counter Behavioral Counter in Verilog Counter using One-Hot State Machine."— Presentation transcript:

1 Counters Discussion D8.3

2 Counters Divide-by-8 Counter Behavioral Counter in Verilog Counter using One-Hot State Machine

3 Divide-by-8 Counter A state diagram for a divide by 8 counter

4 Divide-by-8 Counter A state-transition table s s s s s s s s State Q2 Q1 Q0 D2 D1 D0 Present state Next state

5 Divide-by-8 Counter s s s s s s s s State Q2 Q1 Q0 D2 D1 D0 Present state Next state Q0 Q1 Q2 D0 D1 D2

6 Divide-by-8 Counter Q2 Q1 Q D2 D2 = ~Q2 & Q1 & Q0 | Q2 & ~Q1 | Q2 & ~Q0 s s s s s s s s State Q2 Q1 Q0 D2 D1 D0 Present state Next state

7 Divide-by-8 Counter Q2 Q1 Q D1 D1 = ~Q1 & Q0 | Q1 & ~Q0 s s s s s s s s State Q2 Q1 Q0 D2 D1 D0 Present state Next state

8 Divide-by-8 Counter Q2 Q1 Q D0 D0 = ~Q0 s s s s s s s s State Q2 Q1 Q0 D2 D1 D0 Present state Next state

9 Divide-by-8 Counter A Divide by 8 counter Circuit using D Flip-flops

10 module DFF (D, clk, clr, Q); input clk ; wire clk ; input clr ; wire clr ; input D ; wire D ; output Q ; reg Q ; clk or posedge clr) if(clr == 1) Q <= 0; else Q <= D; endmodule

11 module count3 ( Q,clr,clk ); input clr ; wire clr ; input clk ; wire clk ; output [2:0] Q ; wire [2:0] Q ; wire [2:0] D ; assign D[2] = ~Q[2] & Q[1] & Q[0] | Q[2] & ~Q[1] | Q[2] & ~Q[0]; assign D[1] = ~Q[1] & Q[0] | Q[1] & ~Q[0]; assign D[0] = ~Q[0]; DFF U2(.D(D[2]),.clk(clk),.clr(clr),.Q(Q[2])); DFF U1(.D(D[1]),.clk(clk),.clr(clr),.Q(Q[1])); DFF U0(.D(D[0]),.clk(clk),.clr(clr),.Q(Q[0])); endmodule Q0 Q1 Q2 D0 D1 D2

12 count3 Simulation

13 Counters Divide-by-8 Counter Behavioral Counter in Verilog Counter using One-Hot State Machine

14 3-Bit Counter clk or posedge clr) begin if(clr == 1) Q <= 0; else Q <= Q + 1; end Behavior count3 clr clk Q(2 downto 0)

15 module counter3 (clk, clr, Q ); input clr ; wire clr ; input clk ; wire clk ; output [2:0] Q ; reg [2:0] Q ; // 3-bit counter clk or posedge clr) begin if(clr == 1) Q <= 0; else Q <= Q + 1; end endmodule counter3.v Asynchronous clear Output count increments on rising edge of clk

16 counter3 Simulation

17 Recall Divide-by-8 Counter Use Q2, Q1, Q0 as inputs to a combinational circuit to produce an arbitrary waveform. s s s s s s s s State Q2 Q1 Q0 D2 D1 D0 Present state Next state Q0 Q1 Q2 D0 D1 D2

18 s s s s s s s s State Q2 Q1 Q0 D2 D1 D0 y Example Q2 Q1 Q y = ~Q2 & ~Q1 | Q2 & Q

19 Counters Divide-by-8 Counter Behavioral Counter in Verilog Counter using One-Hot State Machine

20 One-Hot State Machines Instead of using the minimum number of flip-flops (3) to implement the state machine, one-hot encoding uses one flip-flop per state (8) to implement the state machine. Q0 Q1 Q2 D0 D1 D2

21 Why use One-Hot State Machines? Using one-hot encoding or one flip-flop per state (8) will normally simplify the combinational logic at the expense of more flip-flops. Let's see how for the 3-bit counter

22 One-Hot Encoding s s1 s s2 s s3 s s4 s s5 s s6 s s7 s s0 State Q2 Q1 Q0 D[0:7] Present state Next state Think of each state as a flip-flop D[i] = s[i-1] This is just a ring counter!

23 s s s s s s s s State Q2 Q1 Q0 Q2 = s4 | s5 | s6 | s7 Q1 = s2 | s3 | s6 | s7 Q0 = s1 | s3 | s5 | s7 3-bit Counter

24 module cnt3hot1(clk,clr,Q); input clk; input clr; output [2:0] Q; wire [2:0] Q; reg [0:7] s; // 8-bit Ring Counter clk or posedge clr) begin if(clr == 1) s <= 8'b ; else begin s[0] <= s[7]; s[1:7] <= s[0:6]; end //3-bit counter assign Q[2] = s[4] | s[5] | s[6] | s[7]; assign Q[1] = s[2] | s[3] | s[6] | s[7]; assign Q[0] = s[1] | s[3] | s[5] | s[7]; endmodule

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