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CDA 3100 Recitation Week 11.

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Presentation on theme: "CDA 3100 Recitation Week 11."— Presentation transcript:

1 CDA 3100 Recitation Week 11

2 Design a 2-bit counter: Count in the order of 0, 3, 1, 2, 0, 3, 1, 2, … Use a D flip-flop Construct your truth table in the form of a next state diagram That is if input is 00, output is 11

3 Design 4-bit encoder: Truth (Next State)Table
Q1 Q0 D1 D0 1

4 Design 4-bit encoder: K-Map for D1
Q1 Q0 1 D1 = ~Q1

5 Design 4-bit encoder: K-Map for D0
Q1 Q0 1 D0 = (~Q1 * ~Q0) + (Q1 * Q0) = ~(Q1 xor Q0)

6 Verilog Code: Write a Verilog module to have the same effect as the 2-bit counter implemented earlier Just a reminder D1 = ~Q1 D0 = ~(Q1 ^ Q0) You don’t have to reimplement the D flip-flop module, just use the one presented in class module Dff1(D, clk, Q, Qbar); Your module’s prototype will look like: module counter_2_bit(clk, Q);

7 Verilog Code: Dff1 Module Dff1 (D, clk, Q, Qbar); input D, clk; output reg Q, Qbar; initial begin Q = 0; Qbar = 1; end clk) begin #1 Q = D; Qbar = ~Q; endmodule

8 Verilog Code: counter_2_bit
module counter_2_bit(clk, Q); input clk; output [1:0] Q; wire Q1, Q1bar, Q0, Q0bar, D1, D0; assign D0 = ~(Q1 ^ Q0); Dff1 C0(D0, clk, Q0, Q0bar); assign D1 = ~Q1; Dff1 C1(D1, clk, Q1, Q1bar); assign Q[1] = Q1; assign Q[0] = Q0; endmodule

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