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Comp Sci 251 -- instruction encoding 1 Instruction Encoding MIPS machine language Binary encoding of instructions MIPS instruction = 32 bits Three instruction.

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Presentation on theme: "Comp Sci 251 -- instruction encoding 1 Instruction Encoding MIPS machine language Binary encoding of instructions MIPS instruction = 32 bits Three instruction."— Presentation transcript:

1 Comp Sci instruction encoding 1 Instruction Encoding MIPS machine language Binary encoding of instructions MIPS instruction = 32 bits Three instruction formats Different ways of specifying operands

2 Comp Sci instruction encoding 2 Ch. 11 Instruction Encoding Real MIPS Machine Instructions; Mapping pseudo instructions to real ones

3 Comp Sci instruction encoding 3 MIPS instruction formats R-type (register) – Arithmetic/logical (all register operands) – Shift – Jump register I-type (immediate) – Arithmetic/logical (immediate operands) – Load – Store – Conditional branch J-type (jump) – Unconditional jump – Jump and link

4 Comp Sci instruction encoding 4 R-type instruction format Op + funct: instruction ID rs, rt, rd: register operands – 5 bits: long enough for register ID number – rs, rt: source registers – rd: destination register Shamt: shift amount (only used for shifts) – 5 bits: shift amount always in range oprsrtrdshamtfunct 6 bits5 bits 6 bits

5 Comp Sci instruction encoding 5 R-type examples add $5, $6, $7 sll $t6, $t7, 2 #($t6=$14 $t7=$15) op (6)rs (5)rt (5)rd (5)shamt (5)funct (6)

6 Comp Sci instruction encoding 6 R-type example jr $ra op (6)rs (5)rt (5)rd (5)shamt (5)funct (6)

7 Comp Sci instruction encoding 7 I-type instruction format Op: instruction ID rs, rt: register operands Immediate: branch target/immediate operand oprsrdimmediate 6 bits5 bits 16 bits

8 Comp Sci instruction encoding 8 I-type example addi $1, $2, -3 op (6)rs (5)rd (5)immediate (16)

9 Comp Sci instruction encoding 9 I-type examples lw $t0, 12($sp) sw $t0, -12($fp) op (6)rs (5)rt (5)immediate (16)

10 Comp Sci instruction encoding 10 I-type example beq $1, $2, top Immediate: distance to target op (6)rs (5)rt (5)immediate (16) ???? ????

11 Comp Sci instruction encoding 11 PC-relative addressing Used in branch instructions Immediate field contains distance to target – Positive: branch forward – Negative: branch backward – Range: … – Counts number of instructions, not bytes – Distance is measured from next instruction

12 Comp Sci instruction encoding 12 Example top:li $t0, 5 add $t0, $t0, $t1 beq $1, $2, top # distance = -3 sw$t0, x op (6)rs (5)rt (5)immediate (16)

13 Comp Sci instruction encoding 13 PC-relative addressing Q: Why is distance measured from next instruction? A: Fetch-Decode-Execute cycle – Fetch instruction & increment PC (add 4) – Decode instruction: get operands – Execute instruction: compute result, load or store Branch target = PC + 4 * distance

14 Comp Sci instruction encoding 14 J-type instruction format Op: instruction ID Target: (most of) jump address 6 bits26 bits OpTarget

15 Comp Sci instruction encoding 15 J-type examples j bottom# bottom = 0x jal f# f = 0x Op (6)Target (26)

16 Comp Sci instruction encoding 16 Assembly language pseudo-instructions lw $t0, x# address=0x Machine language encoding? 1. Address of x takes up 32 bits – how do we keep it in lw instruction? 2. I-type instruction Immediate field only 16 bits. How do we represent 32 bit immediate field Problem?

17 Comp Sci instruction encoding 17 New instruction Load upper immediate: lui rt, immediate – Immediate operand  high-order 16 bits of rt – 0  low-order 16 bits I-type instruction rtimmediate

18 Comp Sci instruction encoding 18 Use of lui and base register lw $t0, x# address=0x lui $at, 0x1001 lw $t0, 0x0010($at) $at = "assembler temporary" Used to implement pseudo-instructions

19 Comp Sci instruction encoding 19 Another lw problem – index addressing lw $t0, x($t1) # address of x # = 0x Problem? Requirement: x($t1)= address of x + contents of $t1. Problem: (32 bits) (32 bits) Solution: lui $at, 0x1001 add $at, $at, $t1 lw $t0, 0x0010($at)

20 Comp Sci instruction encoding 20 Load immediate pseudo-instruction li $t0, 0x Problem? Solution: lui $at, 0x1234 ori $t0, $at, 0x5678

21 Comp Sci instruction encoding 21 Load immediate w/ small constant li $t0, 5 ori $t0, $0, 5 Only one instruction needed Constant fits into 16-bit immediate field RISC design principle: "make the common case fast"

22 Comp Sci instruction encoding 22 Conditional branch pseudo-instructions MIPS machine language: beq, bne (blez, bgtz, bltz, bgez) All others are pseudo-instructions New instructions: set-on-less-than slt rd, rs, rt if (rs < rt) rd = 1; else rd = 0; slti rt, rs, immed if(rs < immed) rt = 1; else rt = 0;

23 Comp Sci instruction encoding 23 Machine language blt implementation MIPS machine language: beq, bne (blez, bgtz, bltz, bgez) All others are pseudo-instructions Register operands blt $t0, $t1, foo# pseudo instruction # if($t0<$t1) goto foo slt $at, $t0, $t1# if($t0<$t1) $at = 1 bne $at, $0, foo# if($at!=0) goto foo

24 Comp Sci instruction encoding 24 Machine language blt implementation Immediate operand blt $t0, 100, foo slti $at, $t0, 100 bne $at, $0, foo Exercise: ble, bgt, bge

25 Comp Sci instruction encoding 25 Multiplication 32-bit multiply  64-bit product – Where does the product go? – Special-purpose registers: Hi & Lo (each 32 bits) Machine language multiply instruction mult $t0, $t1# $t0 × $t1  Hi:Lo Additional instructions: mfhi $t2# Hi  $t2 mflo $t3# Lo  $t3

26 Comp Sci instruction encoding 26 mul pseudo-instruction # note immediate operand mul $t0, $t1, 123 ori $at, $0, 123 mult $t1, $at mflo $t0

27 Comp Sci instruction encoding 27 Division Hardware division operation produces both – quotient – remainder Machine language divide instruction div $t0, $t1# $t0 / $t1  Lo # $t0 % $t1  Hi

28 Comp Sci instruction encoding 28 div pseudo-instruction # note immediate operand div $t0, $t1, 123 ori $at, $0, 123 div $t1, $at mflo $t0


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