Bitwise Operations Up until now, we’ve done arithmetic ( add, sub,addi ), memory access ( lw and sw ), and branches and jumps. All of these instructions view contents of register as a single quantity (such as a signed or unsigned integer) ° New Perspective: View contents of register as 32 bits rather than as a single 32-bit number Since registers are composed of 32 bits, we may want to access individual bits (or groups of bits) rather than the whole. Introduce two new classes of instructions: Logical Operators Shift Instructions
Logical Operators Two basic logical operators: AND: outputs 1 only if both inputs are 1 OR: outputs 1 if at least one input is 1
Logical Operators Truth Table: standard table listing all possible combinations of inputs and resultant output for each Truth Table for AND and OR A B AND OR0 01 101 Two basic logical operators: –AND: outputs 1 only if both inputs are 1 –OR: outputs 1 if at least one input is 1
Logical Operators Instruction Names: and, or : Both of these expect the third argument to be a register andi, ori : Both of these expect the third argument to be an immediate MIPS Logical Operators are all bitwise, meaning that bit 0 of the output is produced by the respective bit 0’s of the inputs, bit 1 by the bit 1’s, etc.
Uses for Logical Operators Note that ANDing a bit with 0 produces a 0 at the output while ANDing a bit with 1 produces the original bit. This can be used to create a mask. Example: 1011 0110 1010 0100 0011 1101 1001 1010 0000 0000 0000 0000 0000 1111 1111 1111 The result of ANDing these two is: 0000 0000 0000 0000 0000 1101 1001 1010 The second bit string in the example is called a mask. It is used to isolate the rightmost 12 bits of the first bit string by masking out the rest of the string (e.g. setting it to all 0s).
Uses for Logical Operators Thus, the and operator can be used to set certain portions of a bit string to 0s, while leaving the rest alone. In particular, if the first bitstring in the above example were in $t0, then the following instruction would mask it: andi $t0,$t0,0xFFF Similarly, note that OR ing a bit with 1 produces a 1 at the output while OR ing a bit with 0 produces the original bit. This can be used to force certain bits of a string to 1s. For example, if $t0 contains 0x12345678, then after this instruction: ori$t0, $t0, 0xFFFF $t0 contains 0x1234FFFF (e.g. the high-order 16 bits are untouched, while the low-order 16 bits are forced to 1s).
Shift Instructions (1/3) Move (shift) all the bits in a word to the left or right by a number of bits. Example: shift right by 8 bits 0001 0010 0011 0100 0101 0110 0111 1000 0000 0000 0001 0010 0011 0100 0101 0110 Example: shift left by 8 bits 0001 0010 0011 0100 0101 0110 0111 1000 0011 0100 0101 0110 0111 1000 0000 0000
Shift Instructions (2/3) Shift Instruction Syntax: 1 2,3,4 where 1) operation name 2) register that will receive value 3) first operand (register) 4) shift amount (constant <= 32) MIPS shift instructions: 1. sll (shift left logical): shifts left and fills emptied bits with 0s 2. srl (shift right logical): shifts right and fills emptied bits with 0s 3. sra (shift right arithmetic): shifts right and fills emptied bits by sign extending
Uses for Shift Instructions (1/4) Suppose we want to isolate byte 0 (rightmost 8 bits) of a word in $t0. Simply use: andi $t0,$t0,0xFF Suppose we want to isolate byte 1 (bit 15 to bit 8) of a word in $t0. We can use: andi $t0,$t0,0xFF00 but then we still need to shift to the right by 8 bits...
Uses for Shift Instructions (2/4) Could use instead: sll $t0,$t0,16 srl $t0,$t0,24 t0 0001 0010 0011 0100 0101 0110 0111 1000 After sll 0101 0110 0111 1000 0000 0000 0000 0000 After srl 0000 0000 0000 0000 0000 0000 0101 0110
Uses for Shift Instructions (3/4) In binary: Multiplying by 2 is same as shifting left by 1: 11 2 x 10 2 = 110 2 1010 2 x 10 2 = 10100 2 Multiplying by 4 is same as shifting left by 2: 11 2 x 100 2 = 1100 2 1010 2 x 100 2 = 101000 2 Multiplying by 2 n is same as shifting left by n
Uses for Shift Instructions (4/4) Since shifting maybe faster than multiplication, a good compiler usually notices when C code multiplies by a power of 2 and compiles it to a shift instruction: a *= 8; (in C) would compile to: sll $s0,$s0,3 (in MIPS) Likewise, shift right to divide by powers of 2 remember to use sra
The Story so far… We introduced numerous MIPS assembly language instructions. We are now familiar with registers and register usage conventions. We know how to use system calls, basic I/O We have learned how the stack works What is missing? Practice! Practice! Practice!
What Next? We need a more detailed knowledge about the instruction formats to fully appreciate certain restrictions. The functional interface is easy to understand, since it is basically familiar procedural programming We need to understand how the computer interprets the instruction, so that we can transition to the discussion of the MIPS hardware architecture
Machine Language Machine language level programming means that we have to provide the bit encodings for the instructions For example, add $t0, $s1, $s2 represents the 32bit string 00000010001100100100000000100000 Assembly language mnemonics usually translate into one instruction We also have pseudo-instructions that translate into several instructions What does that mean?
Instruction Word Formats Register format Immediate format Jump format op-code rs rt rd shamt funct op-code rs rt immediate value op-code 26 bit current segment address 6 55 16 6 555 5 6 6 26
Register Format (R-Format) Register format op: basic operation of instruction funct: variant of instruction rs: first register source operand rt: second register source operand rd: register destination operand shamt: shift amount op-code rs rt rd shamt funct 6 555 5 6
Watson, the case is clear… add $t0, $s1, $s2 00000010001100100100000000100000 Operation and function field tell the computer to perform an addition 000000 10001 10010 01000 00000 100000 registers $17, $18 and $8 op-code rs rt rd shamt funct 6 555 5 6
0$zero 1$at 2$v0 3$v1 4$a0 5$a1 6$a2 7$a3 8$t0 9$t1 10$t2 11$t3 12$t4 13$t5 14$t6 15$t7 16$s0 17$s1 18$s2 19$s3 20$s4 21$s5 22$s6 23$s7 24$t8 NumberNameValue Registers pass parameters to functions return values from functions $s0-$s7 are callee-saved registers – use these registers for values that must be maintained across function calls. $t0-$t7 are caller saved registers – use these registers in functions
Watson, the case is clear… add $t0, $s1, $s2 00000010001100100100000000100000 source registers $s1=$17 and $s2=$18 and target register $t0=$8 op-code rs rt rd shamt funct 6 555 5 6
R-Format Example Register format (op, funct)=(0,32): add rs=17: first source operand is $s1 rt=18: second source operand is $s2 Rd=8: register destination is $t0 add $t0, $s1, $s2 0 17 18 8 0 32 6 555 5 6
Immediate Format (I-Format) Immediate format op determines the instruction (op <> 0) rs is the source register rt is the destination register 16bit immediate value op rs rt immediate value 6 55 16
I-Format Example Immediate format op=8 means addi rs=29 means source register is $sp rt=29 means $sp is destination register immediate value = 4 addi $sp, $sp, 4 8 29 29 4 6 55 16
Problem The MIPS assembly language has the command andi, an immediate bit-wise and operation We can say li $s0, 0xCDEF1234 to load register $s0 with the content 0xCDEF1234 Why is this strange? In the immediate format, you can only load 16 bits, but the constant is 32 bits!
Pseudo-Instructions li $s0, 0xCDEF1234 is a pseudo-instruction It is a convenient shorthand for lui $at, 0xCDEF ori $s0, $at, 0x1234 The register $at is used here by the assembler; this is the reason why you should not use this register.
Puzzle How can we swap the content of two registers, say $s0 and $s1, without accessing other registers or memory? Solution: xor $s0, $s0, $s1 xor $s1, $s0, $s1 xor $s0, $s0, $s1
MIPS Addressing Modes Immediate addressing Register addressing Base displacement addressing PC-relative addressing address is the sum of the PC and a constant in the instruction Pseudo-direct addressing jump address is 26bits of instruction concatenated with upper bits of PC