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ELEN 468 Lecture 181 ELEN 468 Advanced Logic Design Lecture 18 MIPS Microprocessor.

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Presentation on theme: "ELEN 468 Lecture 181 ELEN 468 Advanced Logic Design Lecture 18 MIPS Microprocessor."— Presentation transcript:

1 ELEN 468 Lecture 181 ELEN 468 Advanced Logic Design Lecture 18 MIPS Microprocessor

2 ELEN 468 Lecture 182 Computer Architecture CISC Complex Instruction Set Computer Intel’s x86, Motorola’s 680x0 RISC Reduced Instruction Set Computer Any computer architecture defined after 1984 MIPS  Microcomputer without Interlocked Pipeline Stages  Millions of Instructions Per Second  Strongly pipelined architecture  DEC’s Alpha, HP’s Precision

3 ELEN 468 Lecture 183 Registers 32 32-bit (word) registers $a0 - $a3: argument registers $v0 - $v1: return values $ra: return address register $sp: stack pointer $fp: frame pointer $gp: global pointer $zero: always equals 0 $s0 - $s7: preserved on a procedural call $t0 - $t9: not preserved by callee on a procedural call

4 ELEN 468 Lecture 184 Arithmetic Operations add a, b, c# a = b + c add $t0, $s1, $s2 sub a, b, c# a = b – c sub $s0, $t0, $t1 Arithmetic operations occur only on registers

5 ELEN 468 Lecture 185 Data Transfer lw $t0, 8($s3) # load $t0 with data from memory # base address in $s3, offset 8 sw $t0, 48($s3) # store word 101 110 10 1001 AddressMemory 0 4 8 12 … … Byte – 8 bits Word – 32 bits Memory in words Address to byte level

6 ELEN 468 Lecture 186 MIPS Fields op: basic operation, also called opcode rs: the first register source operand rt: R-type: the second register source operand I-type: destination register rd: the register destination operand shamt: shift amount in shift instructions funct: selects the specific variant of the operation in op field, also called function code address: offset of memory address in data transfer instructions oprsrtrdshamtfunct oprsrt address R-type I-type 6 bits5 bits 6 bits

7 ELEN 468 Lecture 187 Examples of Machine Code oprsrtrdshamtfunct oprsrtaddress 0181917032 0181917034 351817100 431817100 add $s1, $s2, $s3 sub $s1, $s2, $s3 lw $s1, 100($s2) sw $s1, 100($s2)

8 ELEN 468 Lecture 188 Some Other Instructions beq $s3, $s4, L1# go to branch L1, if equal bne $s3, $s4, L1# go to branch L1, if not equal j L1# jump to branch L1 jr $t0# jump based on $t0 slt $t0, $s1, $s2# set value of $t0 to 1, if less than sll $t2, $s0, 8# reg $t2 = reg $s0 << 8 bits srl $t2, $s0, 8# reg $t2 = reg $s0 >> 8 bits addi $sp, $sp, 4# $sp = $sp + 4 nop# do nothing

9 ELEN 468 Lecture 189 MIPS Addressing Mode Register addressing: the operand is a register Base or displacement addressing: the operand is at the memory whose address is the sum of a register and a constant Immediate addressing: the operand is a constant PC (Program Counter)-relative addressing: address is the sum of PC and a constant in the instruction

10 ELEN 468 Lecture 1810 Steps for MIPS Instructions 1. Fetch instruction from memory 2. Read registers while decoding the instruction 3. Execute the operation or calculate an address 4. Access an operand in data memory (for lw and sw) 5. Write the result into a register

11 ELEN 468 Lecture 1811 Implement Instruction Fetch PC 4 Add Read address Instruction Instruction memory

12 ELEN 468 Lecture 1812 Datapath for R-type Instructions Instruction Read register 1 Read register 2 Write register Write data 5 5 5 Read data 2 Read data 1 Registers 32 Reg_write Control 32 Result ALU

13 ELEN 468 Lecture 1813 Example of Instruction Execution Time InstructionInstruction fetch Register read ALU operation Memory access Register write Total time lw212218 sw21227 R-format (add, sub) 21216 Branch2125

14 ELEN 468 Lecture 1814 Unpipelined vs. Pipelined lw $t1, 8($s1) lw $t2, 16($s2) lw $t3, 12($s3) 24681012141618 IFIDALUMEMWB IFIDALUMEMWB IF lw $t1, 8($s1) lw $t2, 16($s2) lw $t3, 12($s3) IF: Instruction fetch ID: Instruction decode and read register ALU: Execution or address calculation MEM: Memory access WB: Write back to reg IFIDALUMEMWB IFIDALUMEMWB IFIDALUMEMWB

15 ELEN 468 Lecture 1815 Instruction Sets for Pipelining All instructions have the same length There are only a few instruction formats Memory operands only appear in loads or stores Operands must be aligned in memory

16 ELEN 468 Lecture 1816 Pipeline Hazards Situations when the next instruction cannot execute in the following clock cycle Structural hazards Control hazards Data hazards

17 ELEN 468 Lecture 1817 Structural Hazards Hardware cannot support the combined instructions that we want to execute in the same clock cycle Example: if there is only one memory, then memory access and instruction fetch cannot be executed simultaneously Solution: add hardware

18 ELEN 468 Lecture 1818 Control Hazards Decision-making depends on the result of an instruction that has not been finished Example: PC following a branch instruction depends if branch is taken or not Solutions Predict: execute next instruction anyway, if branch is taken, retract the decision Dynamic prediction based on smart guess

19 ELEN 468 Lecture 1819 Data Hazards An instruction cannot be executed until a data is available from another instruction Example: add $s0, $t1, $t2 sub $t2, $s0, $t3 Solution: Bypassing: result can be fed to next instruction execution without loading to a register

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