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S. Barua – CPSC 440 CHAPTER 2 INSTRUCTIONS: LANGUAGE OF THE COMPUTER Goals – To get familiar with.

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Presentation on theme: "S. Barua – CPSC 440 CHAPTER 2 INSTRUCTIONS: LANGUAGE OF THE COMPUTER Goals – To get familiar with."— Presentation transcript:

1 S. Barua – CPSC 440 CHAPTER 2 INSTRUCTIONS: LANGUAGE OF THE COMPUTER Goals – To get familiar with MIPS assembly language – To introduce stored program concept – To explain how MIPS instructions are represented in machine language – To contrast MIPS with other architectures – To illustrate basic instruction set design principles

2 S. Barua – CPSC 440 MIPS REGISTERS MIPS employs 32, 32-bit general purpose registers and 32 floating-point registers. Groups of 32 bits form a word in MIPS.

3 S. Barua – CPSC 440 MIPS General Purpose Registers Register Numbers & Usage Zero register $zero 0 Contains the constant value 0 Assembler Temporary $at 1 Reserved for the assembler to handle pseudoinstructions Return value registers $v0 - $v1 2 - 3 For values for results and expression evaluation Argument registers $a0 - $a3 4 - 7 For arguments Temporary registers $t0 - $t7 8 - 15 For temporaries Saved registers $s0 - $s7 16 - 23 As saved registers Temporary registers $t8 - $t9 24 - 25 For temporaries $k0 - $k1 26 - 27 Reserved for the operating system Global pointer $gp 28 As global pointer Stack pointer $sp 29 As stack pointer Frame pointer $fp 30 As frame pointer Return address register $ra 31 To save return address

4 S. Barua – CPSC 440 In addition to the 32 general purpose registers, two additional 32-bit registers, namely, the Hi register and the Lo register are also available. These registers are used as follows: For multiplication:Hi Lo  Result of multiplication (64-bit product) For division:Lo  Quotient Hi  Remainder Floating point coprocessor operates on single precision (32-bit) and double precision (64-bit) floating point numbers. The coprocessor registers are numbered as $f0 - $f31.

5 S. Barua – CPSC 440 MIPS MEMORY ORGANIZATION Memory is byte organized. So sequential words differ by 4 memory locations. Words must always start at addresses that are multiples of 4 in MIPS (alignment restriction).

6 S. Barua – CPSC 440 Memory Byte Memory Word 08 bits of data 0 32 bits of data 18 bits of data 4 32 bits of data 28 bits of data 8 32 bits of data 38 bits of data 12 32 bits of data 48 bits of data. 58 bits of data. 68 bits of data 78 bits of data. 2 32 bytes with byte addresses from 0 to 2 32  1 2 30 words with word addresses from 0, 4, 8,... 2 32  4 Words are aligned

7 S. Barua – CPSC 440 MIPS INSTRUCTIONS MIPS instructions are grouped as follows: – Arithmetic and logical instructions Add, subtract, multiply, divide, and, or, shift left, shift right – Data transfer instructions load, store – Conditional branch instructions branch, set – Unconditional jump jump – Floating point instructions – Exception and interrupt instructions

8 S. Barua – CPSC 440 Arithmetic Instruction (All instructions have 3 operands,with destination being first) add $s2, $s1, $s5#$s2 = $s1 + $s5 sub $s2, $s1, $s5#$s2 = $s1  $s5 Example Consider the C code segment:A = B + C + D; E = F  A; MIPS code:

9 S. Barua – CPSC 440 Data Transfer Instructions (load and store) lw $s6, 128($s4) #$s6 = Memory[$s4 + 128] sw $s6, 128($s4) #Memory[$s4 + 128] = $s6 Example Consider the C code: A[8] = h + A[8]; MIPS code:

10 S. Barua – CPSC 440 Conditional Branch beq $s3, $s5, L#If ($s3 = $s5) go to L bne $s3, $s5, L#If ($s3  $s5) go to L slt $s3, $s5, $s6#If ($s5 < $s6), then set $s3 to 1, else set $s3 to 0 Example Consider the C code: if (i == j) h = i + j; MIPS code:

11 S. Barua – CPSC 440 Unconditional Jump j L#go to target address L jal L#$ra = return address and go to subprogram located at L jr $ra#return to the address specified in $ra Example Consider the C code segment:if (i != j) h = i + j; else h = i  j; MIPS code:

12 S. Barua – CPSC 440 OPERANDS OF THE COMPUTER HARDWARE Programs in high-level language employ variables as operands. But operands of arithmetic operations in MIPS must be registers. The compiler associates variables with registers and allocates data structures such as arrays to consecutive memory locations. If the program has more variables than the number of registers in the machine used to run the program, then the compiler will place only the most frequently used variables in the registers and the rest are placed in memory (register spilling). Since data in registers are both faster to access and easier to use, to achieve high performance, MIPS compilers must use registers efficiently.

13 S. Barua – CPSC 440 SUPPORTING PROCEDURES IN COMPUTER HARDWARE Registers are the fastest place to hold data in a computer, MIPS software allocates the following registers for procedure calling: $a0 - $a3:Argument registers in which to pass parameters $v0 - $v1:Value registers in which to return values $ra:Return address register to return to the point of origin If the compiler needs more registers for a procedure, the stack can be used (register spilling). The stack is pointed to by $sp. The traditional push and pop instructions are implemented in MIPS using the sw and lw instructions. The stack grows from higher addresses to lower addresses.

14 S. Barua – CPSC 440 NESTED PROCEDURES Example In an application program, procedure A calls procedure B and procedure B calls procedure C. Give the MIPS code to implement the calling protocol.

15 S. Barua – CPSC 440 MIPS INSTRUCTION FORMATS R-Format 31 0 op rs rt rd shamtfunct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits whereop  opcode rs  source register 1(register numbers between 0 and 31) rt  source register 2(register numbers between 0 and 31) rd  destination register(register numbers between 0 and 31) shamt  shift amount funct  function code Example instructions (partial list) : add, sub, mult, div, sll, srl

16 S. Barua – CPSC 440 I-Format (Transfer, branch, immediate format) 31 0 oprs rt address/immediate 6 bits 5 bits 5 bits 16 bits For lw, op  opcode rs  base register (register numbers between 0 and 31) rt  destination register (register numbers between 0 and 31) For sw, op  opcode rs  base register(register numbers between 0 and 31) rt  source register(register numbers between 0 and 31)

17 S. Barua – CPSC 440 J-Format (Jump instruction format) 31 0 op target address 6 bits 26 bits

18 S. Barua – CPSC 440 MIPS ADDRESSING MODES – Register addressing – Base (displacement) addressing – Immediate addressing – PC relative addressing – Pseudodirect addressing - 26-bit address given by the jump instruction (J-format) is concatenated with the upper 4 bits of PC

19 S. Barua – CPSC 440 Example Give the MIPS code for the following procedure written in C. swap (int v[ ], int k) { int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; }

20 S. Barua – CPSC 440 STORED PROGRAM CONCEPT Modern computers are built on two principles: 1. Instructions are represented as numbers (machine language) 2. Programs (application programs, compilers, editors, etc.) are stored in memory to be read or written just like data. These two principles form the basis of the stored program concept.

21 S. Barua – CPSC 440 ADVANCES IN 80X86 PROCESSORS 1978: The Intel 8086 was announced (16-bit architecture) 1980: The 8087 floating point coprocessor is added 1982: The 80286 increased the address space to 24 bits, new instructions added 1985: The 80386 extends to 32 bits, new addressing modes added 1989 - 1995: The 80486, Pentium, and Pentium Pro introduced New instructions, mostly designed for higher performance are added 1997: MMX added 1998: Pentium II, Pentium II Xeon, Celeron 1999: Pentium III 2001: Itanium 2002: Pentium 4

22 S. Barua – CPSC 440 SUMMARY Design goals: – Maximize performance Provide more powerful operations - Goal is to reduce the number of instructions executed. Danger is a higher CPI or a slower cycle time – Minimize cost – Reduce design time

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