1. UNIT 14 DERIVATION OF STATE GRAPHS AND TABLES Spring 2011

2. © Iris H.-R. Jiang Derivation of State Graphs and Tables  Contents  Case studies: sequence detectors  Guidelines for construction of state graphs  Serial data code conversion  Alphanumeric state graph notation  Reading  Unit 14 Derivation of state graphs & tables 2 Basic unit Unit 11: Latch & FFs Simple sequential Ckt Unit 12: Registers & Counters Complex sequential Ckt Units 13-15: FSM Put it all together Unit 16: Summary

3. © Iris H.-R. Jiang Designing a Sequential Circuit  Given the specification of a sequential circuit  Design procedure: 1. Construct a state table or state graph (Unit 14) 2. Simplify (Unit 15) 3. Derive FF input equations and output equations (Unit 12) Derivation of state graphs & tables 3 Basic unit Unit 11: Latch & FFs Simple sequential Ckt Unit 12: Registers & Counters Complex sequential Ckt Units 13-15: FSM Put it all together Unit 16: Summary

4. Sequence Detectors 4 Derivation of state graphs & tables

5. © Iris H.-R. Jiang Case I (1/2)  Examine groups of 4 consecutive inputs & produce an output  Reset after every 4 inputs  e.g., X = 0101 0010 1001 0100 Z = 0001 0000 0001 0000  Observation:  Typical sequence  Partial state graph Derivation of state graphs & tables 5 0101 1001 Detector XZ Clock 0/0 S0S0 S1S1 S3S3 1/0 S2S2 0/0 1/0 S4S4 0/0 1/1 X = 0101 X = 1001 Input/output

6. © Iris H.-R. Jiang Case I (2/2)  Complete state graph Derivation of state graphs & tables 6 0/0 S0S0 S1S1 S3S3 1/0 S2S2 0/0 1/0 S4S4 0/0 1/1 S5S5 0/0 S6S6 1/0 0/0 1/0

7. © Iris H.-R. Jiang Case II (1/4)  Examine groups of 3 consecutive inputs & produce an output  No reset  e.g., X = 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 Z = 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0  State graph (Mealy)  S 0 : initial, S 1 : get …1, S 2 : get …10 Derivation of state graphs & tables 7 101 Detector XZ Clock S0S0 S1S1 0/0 1/0 S2S2 1/1 0/0 S0S0 S1S1 1/0 S2S2 1/1 0/0 1/0 S0S0 S1S1 0/0 1/0

8. © Iris H.-R. Jiang Case II (2/4)  State table Derivation of state graphs & tables 8 X A + =X'B 1 0 0 00 01 11 10 X 0 10 0 X 0 AB X B + =X 1 0 0 00 01 11 10 X 0 01 1 X 1 AB X Z=XA 1 0 0 00 01 11 10 X 0 00 0 X 1 AB Present state S0S1S2S0S1S2 Next state X = 0 X = 1 S0S2S0S0S2S0 S1S1S1S1S1S1 Present output X = 0 X = 1 000000 001001  State maps AB 00 01 10 11 A + B + X = 0 X = 1 00 10 00 XX 01 XX Z X = 0 X = 1 000X000X 001X001X

9. © Iris H.-R. Jiang Case II (3/4)  State maps  Realize it 9 CK A'A'A D B'B'B D Clock X Z Derivation of state graphs & tables Q: Check by yourself X = 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 Z = 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 ??

10. © Iris H.-R. Jiang Case II (4/4)  Moore?  S 0 : initial, S 1 : get …1, S 2 : get …10, S 3 : get …101 Derivation of state graphs & tables 10 0 1 0 S00S00 S10S10 S20S20 S31S31 1 0 1 0 S00S00 S10S10 S20S20 S31S31 1 1 0 1 0 0 1 0 S00S00 S10S10 S20S20 Present state S0S1S2S3S0S1S2S3 Next state X = 0 X = 1 S0S2S0S2S0S2S0S2 S1S1S3S1S1S1S3S1 Present output 00010001 AB 00 01 10 11 A + B + X = 0 X = 1 00 10 00 10 01 11 01 Z 00010001

11. © Iris H.-R. Jiang Case III (1/2)  010 & 1001 detector  e.g., X = 0 0 1 0 1 0 0 1 0 0 0 1 0 0 1 1 a b c d e f Z = 0 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0  State assignment Derivation of state graphs & tables 11 010 1001 Detector XZ Clock  State for “1001”  Complete  State for “010”

12. © Iris H.-R. Jiang Case III (2/2) Derivation of state graphs & tables 12 0/0 S0S0 S1S1 S3S3 S2S2 1/0 0/1 1/0 S4S4 0/0 1/0 b c S5S5 d 0/0 1/1 e ? 0/0 S0S0 S1S1 S3S3 S2S2 1/0 0/1 1/0 a 0/0 S0S0 S1S1 S3S3 S2S2 1/0 0/1 1/0 S4S4 0/0 1/0 b c S5S5 g 0/01/1 f 1/0 e h 0/0 i  State for “1001”  Complete  State for “010”

13. © Iris H.-R. Jiang Case IV (1/2)  Specifications  Z = 1 if total # of 1’s is odd and at least two consecutive 0’s have been received  e.g., X = 1 0 1 1 0 0 1 1 Z =(0) 0 0 0 0 0 1 0 1  State assignment  Initial state and state for 1’s  State for 0’s Derivation of state graphs & tables 13 Reset or even 1’s 1 S00S00 S10S10 1 Odd 1’s

14. © Iris H.-R. Jiang Case IV (2/2)  State graph 14 Reset or even 1’s 1 S00S00 S10S10 1 Odd 1’s 1 S00S00 S10S10 1 S30S30 S41S41 S20S20 1 1a 0 0 1 S00S00 S10S10 1 S30S30 S41S41 S20S20 1 1 b 0 0 S50S50 0 0 c g d e f Even 1’sOdd 1’s 00 1 1 Initial state and state for 1’s Derivation of state graphs & tables

15. Guidelines for State Graph Construction 15 Derivation of state graphs & tables

16. © Iris H.-R. Jiang Guidelines for State Graphs Construction  Steps 1. Construct sample sequences to help you understand the problem 2. Determine under what conditions it should reset 3. If only one or two sequences leads to a nonzero output, construct a partial state graph Another way, determine what sequences or groups of sequences must be remembered by the circuit and set up states accordingly 4. Each time you add an arrow to the state graph, determine whether it can go to one of the previously defined states or whether a new state must added 5. Check your graph to make sure there is one and only one path leaving each state for each combination of values of the input variables 6. When your graph is complete, verify it by applying the input sequences formulated in step 1 Derivation of state graphs & tables 16

17. Serial Data Code Conversion 17 Derivation of state graphs & tables

18. © Iris H.-R. Jiang Serial Data Transmission  Coding schemes Derivation of state graphs & tables 18 Receiver Serial Data Clock Clock Recovery Circuit TransmitterReceiver Serial Data Clock Bit Sequence NRZ NRZI RZ Manchester Clock 01110010 1 bit time Use 2 cables (not good) NRZ: Non-return-to-zero NRZI: Non-return-to-zero-inverted RZ: Return-to-zero 0  0; 1  1 0  d - ; 1  ~d - 0  0; 1  10 0  01; 1  10 Transmitter

19. © Iris H.-R. Jiang Mealy?  Mealy:  Output depends on Current state (synchronous) Input (maybe asynchronous)  Fewer states Derivation of state graphs & tables 19 Conversion Network Z Manchester data NRZ data Clock2 X S0S0 S1S1 S2S2 1/1 1/00/1 0/0 Present state S0S1S2S0S1S2 Next state X = 0 X = 1 S1S0-S1S0- S2-S0S2-S0 output (Z) X = 0 X = 1 01-01- 1-01-0 NRZ (X) Manchester (ideal) Clock2 State Z (Actual) 1 clock period S0S0 S1S1 S0S0 S2S2 S0S0 S2S2 S0S0 S2S2 S0S0 S1S1 S0S0 S1S1 S0S0 S2S2 S0S0 S1S1 0110101001011001 0011111100001100 Glitch: false output Bit sequence 01110010 NRZ: combintaion of double 0’s & double 1’s Starting state: S 0

20. © Iris H.-R. Jiang Moore?  Moore:  Output only depends on Current state (synchronous)  More states (in general)  1 clock period delay Derivation of state graphs & tables 20 Clock2 State Z X (NRZ) 1 clock period S0S0 S1S1 S2S2 S3S3 S0S0 S3S3 S0S0 S3S3 S0S0 S1S1 S2S2 S1S1 S2S2 S3S3 S0S0 S1S1 0011111100001100 0011010100101100 S31S31 S21S21 S00S00 0 1 1 S10S10 100 Present state S0S1S2S3S0S1S2S3 Next state X = 0 X = 1 S1S2S1-S1S2S1- S3-S3S0S3-S3S0 Present output (Z) 00110011 Conversion Network Z Manchester data NRZ data Clock2 X Starting states: S 0, S 2

21. Alphanumeric State Graph Notation 21 Derivation of state graphs & tables

22. © Iris H.-R. Jiang Alphanumeric State Graph Notation  When a sequential circuit has several inputs, label the state graph arcs with alphanumeric input variable names instead of 0’s and 1’s  e.g., 2 inputs: F: forward, R: reverse  Decide priority. E.g. F has higher priority than R Derivation of state graphs & tables 22 S0Z1S0Z1 R S2Z3S2Z3 S1Z2S1Z2 R R F FF Incomplete S0Z1S0Z1 F'R S2Z3S2Z3 S1Z2S1Z2 F FF F'R' Present state S0S1S2S0S1S2 Next state FR = 00 01 10 11 S 0 S 2 S 1 S 1 S 1 S 0 S 2 S 2 S 2 S 1 S 0 S 0 Output Z 1 Z 2 Z 3 1 0 0 0 1 0 0 0 1

23. © Iris H.-R. Jiang Complete?  Completely specified state graph  OR together all input labels on arcs emanating from a state, the result can reduce to 1 Cover all conditions: F + F'R +F'R' = F + F' = 1  AND together any pair of input labels on arcs emanating from a state, the result can reduce to 0 Only one arc is valid: F·F'R = 0, F·F'R' = 0, F'R·F'R' = 0  Notation in state graph  X 1 X' 4 /Z 2 Z 3  1--0/0110  -/Z 1  ----/1000 For any combination of input values… Derivation of state graphs & tables 23 S0Z1S0Z1 F'R S2Z3S2Z3 S1Z2S1Z2 F FF F'R'

24. © Iris H.-R. Jiang Homework for Unit 14  14.26, 14.32, 14.41, 14.46 Derivation of state graphs & tables 24