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**COE 202: Digital Logic Design Sequential Circuits Part 3**

Courtesy of Dr. Ahmad Almulhem KFUPM

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**Objectives Design of Synchronous Sequential Circuits**

Procedure Examples Important Design Concepts State Reduction and Assignment KFUPM

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**Design of Synchronous Sequential Circuits**

The design of a clocked sequential circuit starts from a set of specifications and ends with a logic diagram (Analysis reversed!) Building blocks: flip-flops, combinational logic Need to choose type and number of flip-flops Need to design combinational logic together with flip-flops to produce the required behavior The combinational part is flip-flop input equations output equations KFUPM

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**Design of Synchronous Sequential Circuits**

Design Procedure: Obtain a state diagram from the word description State reduction if necessary Obtain State Table State Assignment Choose type of flip-flops Use FF’s excitation table to complete the table Derive state equations Obtain the FF input equations and the output equations Use K-Maps Draw the circuit diagram KFUPM

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**Step1: Obtaining the State Diagram**

A very important step in the design procedure. Requires experience! Example: Design a circuit that detects a sequence of three consecutive 1’s in a string of bits coming through an input line (serial bit stream) KFUPM

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**Step1: Obtaining the State Diagram**

A very important step in the design procedure. Requires experience! Example: Design a circuit that detects a sequence of three consecutive 1’s in a string of bits coming through an input line (serial bit stream) KFUPM

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**Step2: Obtaining the State Table**

Assign binary codes for the states We choose 2 D-FF Next state specifies what should be the input to each FF Example: Design a circuit that detects a sequence of three consecutive 1’s in a string of bits coming through an input line (serial bit stream) KFUPM

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**Step3: Obtaining the State Equations**

Using K-Maps A(t + 1) = DA = ∑(3,5,7) = A x + B x B(t + 1) = DB = ∑(1,5,7) = A x + B’ x y = ∑(6,7) = A B Example: Design a circuit that detects a sequence of three consecutive 1’s in a string of bits coming through an input line (serial bit stream) KFUPM

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Step4: Draw Circuits Using K-Maps A(t + 1) = DA = ∑(3,5,7) = A x + B x B(t + 1) = DB = ∑(1,5,7) = A x + B’ x y = ∑(6,7) = A B Example: Design a circuit that detects a sequence of three consecutive 1’s in a string of bits coming through an input line (serial bit stream) KFUPM

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**Design with Other types of FF**

In designing with D-FFs, the input equations are obtained from the next state (simple!) It is not the case when using JK-FF and T-FF ! Excitation Table: Lists the required inputs that will cause certain transitions. Characteristic tables used for analysis, while excitation tables used for design + + KFUPM

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**Example 1 Problem: Design of A Sequence Recognizer**

Design a circuit that reads as inputs continuous bits, and generates an output of ‘1’ if the sequence (1011) is detected X Y Input Output KFUPM

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**Sequence to be detected:1011**

Example 1 (cont.) Sequence to be detected:1011 Step1: State Diagram KFUPM

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Example 1 (cont.) Step 2: State Table OR KFUPM

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**Example 1 (cont.) Step 2: State Table state assignment Q: How many FF?**

log2(no. of states) KFUPM

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**Example 1 (cont.) Step 2: State Table choose FF**

In this example, lets use JK–FF for A and D-FF for B KFUPM

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**JK–FF excitation table**

Example 1 (cont.) Step 2: State Table complete state table use excitation tables for JK–FF and D-FF D–FF excitation table Next State output JK–FF excitation table KFUPM

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**Example 1 (cont.) Step 3: State Equations use k-map JA = BX’**

KA = BX + B’X’ DB = X Y = ABX’ KFUPM

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**Example 1 (cont.) Step 4: Draw Circuit JA = BX’ KA = BX + B’X’ DB = X**

Y = ABX’ KFUPM

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**Example 2 Problem: Design of A 3-bit Counter**

Design a circuit that counts in binary form as follows 000, 001, 010, … 111, 000, 001, … KFUPM

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**Example 2 (cont.) Step1: State Diagram The outputs = the states**

Where is the input? What is the type of this sequential circuit? KFUPM

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**Example 2 (cont.) Step2: State Table No need for state assignment here**

KFUPM

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**Example 2 (cont.) Step2: State Table We choose T-FF**

T–FF excitation table KFUPM

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Example 2 (cont.) Step3: State Equations KFUPM

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**Example 2 (cont.) Step4: Draw Circuit TA0 = 1 TA1 = A0 TA2 = A1A0**

KFUPM

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**Example 3 Problem: Design of A Sequence Recognizer**

Design a Moore machine to detect the sequence (111). The circuit has one input (X) and one output (Z). KFUPM

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**Sequence to be detected:111**

Example 3 (cont.) Sequence to be detected:111 Step1: State Diagram S0/0 S1/0 S2/0 S3/1 1 KFUPM

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**Example 3 (cont.) Step2: State Table Use binary encoding**

Use JK-FF and D-FF S0/0 S1/0 S2/0 S3/1 1 KFUPM

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**Example 3 (cont.) Step4: Draw Circuit For step3, use k-maps as usual**

JA = XB KA = X’ DB = X(A+B) Z = A.B KFUPM

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**Example 3 (cont.) Timing Diagram (verification)**

Question: Does it detect 111 ? KFUPM

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Example 4 Problem: Design a traffic light controller for a 2-way intersection. In each way, there is a sensor and a light N Traffic Action EW only EW Signal green NS Signal red NS only NS Signal green EW Signal red EW & NS Alternate No traffic Previous state W E S KFUPM

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**Example 4 (cont.) Step1: State Diagram 11, 10 NS / 01 EW / 10 00, 01**

00, 10 11, 01 INPUTS Sensors X1, X0 X0: car coming on NS X1 : car coming on EW OUTPUTS Light S1, S0 S0 : NS is green S1 : EW is green STATES NS: NS is green EW: EW is green KFUPM

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**Example 4 (cont.) Exercise: Complete the design using: D-FF JK-FF T-FF**

KFUPM

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Example 5 Problem: Design Up/Down counter with Enable Design a sequential circuit with two JK flip-flops A and B and two inputs X and E. If E = 0, the circuit remains in the same state, regardless of the input X. When E = 1 and X = 1, the circuit goes through the state transitions from 00 to 01 to 10 to 11, back to 00, and then repeats. When E = 1 and X = 0, the circuit goes through the state transitions from 00 to 11 to 10 to 01, back to 00 and then repeats. KFUPM

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**Example 5 (cont.) Present State Inputs Next State FF Inputs A B E X JA**

KA JB KB 1 00 01 10 11 KFUPM

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**Example 5 (cont.) Y X E JA = BEX + B’EX’ KA = BEX + B’EX’ JB = E**

00 01 11 10 1 x EX AB 00 01 11 10 x 1 Y X JA C A A’ KA E clock JB B B’ KB JA = BEX + B’EX’ KA = BEX + B’EX’ EX AB 00 01 11 10 1 x EX AB 00 01 11 10 x 1 X JB = E KB = E KFUPM

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**More Design Examples More design examples can be found at Homework 5**

Textbook Course CD Google KFUPM

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State Reduction Two sequential circuits may exhibits the same input-output behavior, but have a different number of states State Reduction: The process of reducing the number of states, while keeping the input-output behavior unchanged. It results in less Flip flops It may increase the combinational logic! KFUPM

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**State Reduction (Example)**

Is it possible to reduce this FSM? How many states? How many input/outputs? Notes: we use letters to denote states rather than binary codes we only consider input/output sequence and transitions KFUPM

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**State Reduction (Example)**

Step 1: get the state table KFUPM

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**State Reduction (Example)**

Step 1: get the state table Step 2: find similar states e and g are equivalent states remove g and replace it with e KFUPM

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**State Reduction (Example)**

Step 1: get the state table Step 2: find similar states e and g are equivalent states remove g and replace it with e KFUPM

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**State Reduction (Example)**

Step 1: get the state table Step 2: find similar states d and f are equivalent states remove f and replace it with d KFUPM

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**State Reduction (Example)**

Step 1: get the state table Step 2: find similar states d and f are equivalent states remove f and replace it with d KFUPM

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**State Reduction (Example)**

Reduced FSM Verify sequence: State a b c d e f g input 1 output KFUPM

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State Assignmnet State Assignment: Assign unique binary codes to the states For m states, we need log2 m bits (FF) Example Three Possible Assignments: KFUPM

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**Summary To design a synchronous sequential circuit:**

Obtain a state diagram State reduction if necessary Obtain State Table State Assignment Choose type of flip-flops Use FF’s excitation table to complete the table Derive state equations Use K-Maps Obtain the FF input equations and the output equations Draw the circuit diagram KFUPM

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CSCE 211: Digital Logic Design

CSCE 211: Digital Logic Design

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