Download presentation

1
**STATE DIAGRAM AND STATE TABLES**

2
**Derivation of State Graphs**

9/2/2012 – ECE 3561 Lect 6 Problem Statement specifies the desired relationship between the input and output sequences. Sometimes called the specification. First step is to translate this specification into a state table or state graph. In the HDL world, there is a style that allows creation of the next state specification that does not require either a state graph or state table. Copyright Joanne DeGroat, ECE, OSU

3
**State diagram State transition diagram**

a circle: a state a directed lines connecting the circles: the transition between the states Each directed line is labeled “inputs/outputs” state: A B input: x

4
**Flip-Flop Input Equations**

The part of circuit that generates the inputs to flip-flops Also called excitation functions DA = Ax +Bx DB = A'x The output equations to fully describe the sequential circuit y = (A+B)x' Ax +Bx Ax Bx A 'x A+B

5
**Analysis with D flip-flops**

The input equation DA=A⊕x⊕y The state equation A(t+1)=A⊕x⊕y

6
**Analysis with JK flip-flops**

Determine the flip-flop input function in terms of the present state and input variables Used the corresponding flip-flop characteristic table to determine the next state Fig. 5-18 Sequential circuit with JK flip-flop JA = B KA= Bx' JB = x ' KB = A'x + Ax '

7
State Table for Fig. 5-18 JA = B, KA= Bx' JB = x ', KB = A'x + Ax '

8
**Method 1 State Transition Diagram for Fig. 5-18**

The characteristic equation of JK FF is State equation for A and B : ,

9
**Method 2 State Transition Diagram for Fig. 5-18**

x AB 1 AB’ A(t +1) A’B Ax Using K-map, we also can derive A(t+1). A(t +1)=A ’B+AB ’+Ax

10
**Analysis with T Flip-Flops**

The characteristic equation Q(t+1)= T⊕Q = TQ'+T'Q

11
**A Sequence Detector Example**

9/2/2012 – ECE 3561 Lect 6 The specification The circuit will examine a string of 0’s and 1’s applied serially, once per clock, to the X input and produce a 1 only when the prescribed input sequence occurs. Any sequence ending in 101 will produce and output of Z=1 coincident with the last 1 input. The circuit does not reset when a 1 output occurs so when ever a 101 is in the data stream a 1 is output coincident with the last 1. Copyright Joanne DeGroat, ECE, OSU

12
**General Form of the circuit**

9/2/2012 – ECE 3561 Lect 6 The circuit has the general form X – serial input stream Z – serial output stream Clk – the clock Copyright Joanne DeGroat, ECE, OSU

13
**Start construction of the graph.**

9/2/2012 – ECE 3561 Lect 6 Choose a starting state and a meaning for that state. The starting state is typically a reset state. Here meaning of starting state can be The system has been reset and this is the initial state A sequence of 2 or more 0’s has been received Copyright Joanne DeGroat, ECE, OSU

14
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

Add the next state 9/2/2012 – ECE 3561 Lect 6 Now add state S1 Meaning – a sequence of 0…01 has been received when coming from state S0 Meaning – the first 1 has been received. Copyright Joanne DeGroat, ECE, OSU

15
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

Transitions from S1 9/2/2012 – ECE 3561 Lect 6 What happens when in S1 A 0 input causes transition to a new state S2 with new meaning A 1 keeps you in S1 where the first 1 of a possible 101 sequence has occurred. Copyright Joanne DeGroat, ECE, OSU

16
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

State S2 9/2/2012 – ECE 3561 Lect 6 State S2 – what is the meaning of being here? When transition is from S1 it means we have receive an input stream of xxx10. Copyright Joanne DeGroat, ECE, OSU

17
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

Transitions from S2 9/2/2012 – ECE 3561 Lect 6 Are currently in S2 A 1 arrives and now have a sequence of 101 Action – Output a 1 and have the first 1 of a new sequence, i.e., transition to S1 A 0 arrives – now have a sequence of 100 Action – Move back to state S0 where you do not even have the start of a sequence, i.e., one or more 0 inputs. Copyright Joanne DeGroat, ECE, OSU

18
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

The full state diagram 9/2/2012 – ECE 3561 Lect 6 The now completed state diagram This can now be used to generate a state table – more on that later Copyright Joanne DeGroat, ECE, OSU

19
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

Another example 9/2/2012 – ECE 3561 Lect 6 Problem Statement: The circuit has the same form as before and shown below. The circuit will detect input sequences that end in 010 or When a sequence is detected the output Z is 1, otherwise Z is 0. Copyright Joanne DeGroat, ECE, OSU

20
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

The initial state 9/2/2012 – ECE 3561 Lect 6 The RESET state – have no inputs yet Then if you have a 0 input the output is 0 – transition to S1 If you have a 1 input the output is 0 and transition to S2 Copyright Joanne DeGroat, ECE, OSU

21
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

Meaning of states 9/2/2012 – ECE 3561 Lect 6 S0 – Reset S1 – 0 but not 10 S4 – 1 but not 01 Copyright Joanne DeGroat, ECE, OSU

22
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

More states 9/2/2012 – ECE 3561 Lect 6 Add S2 having meaning that a 01 sequence has been received. Add S3 having meaning that the sequence 10 has been received Copyright Joanne DeGroat, ECE, OSU

23
**Meaning of states after S2 S3**

9/2/2012 – ECE 3561 Lect 6 S0 – Reset S1 – 0 but not 10 S2 – Sequence of 01 S3 – Sequence of 10 S4 – 1 but not 01 Copyright Joanne DeGroat, ECE, OSU

24
**Consider inputs when in S2, S3**

9/2/2012 – ECE 3561 Lect 6 In S2 (01) and get a 0 – Transition to S3 (10) – output a 1 In S3 (10) and get a 1 – Transition to S2 (01) Copyright Joanne DeGroat, ECE, OSU

25
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

Add a new state S5 9/2/2012 – ECE 3561 Lect 6 S5 – Have received input sequence 100 Copyright Joanne DeGroat, ECE, OSU

26
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

When in S5 9/2/2012 – ECE 3561 Lect 6 In S5 Input of a 1 means you have had a input of 1001 so transition to S2 as the input sequence now ends in 01 while Z is 1. Copyright Joanne DeGroat, ECE, OSU

27
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

Add other transitions 9/2/2012 – ECE 3561 Lect 6 Complete the transitions not yet covered Each state should have an output transition for both a 0 and a 1. Copyright Joanne DeGroat, ECE, OSU

28
**The meaning of the states**

9/2/2012 – ECE 3561 Lect 6 S0 – Reset S1 – 0 (but not 10) S2 – Sequence of 01 S3 – Sequence of 10 S4 – 1 (but not 01) S5 – Sequence of 100 Copyright Joanne DeGroat, ECE, OSU

29
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

Guidelines 9/2/2012 – ECE 3561 Lect 6 Guidelines for Construction of State Graphs First, construct some sample input and output sequences to make sure you understand the problem (ref slides 5 and 13) Determine under what conditions the circuit is in reset state. If only one or two sequences lead to a 1 output construct a partial state graph. OR determine what sequences or groups of sequences must be remembered When adding transitions see if you transition to a defined state or a new state is to be added Make sure all state have a transition for both a 0 and a 1 but only 1! Add annotation or create a table to expound the meaning of each state. Copyright Joanne DeGroat, ECE, OSU

30
MOORE MACHINE

31
**Mealy Machine vs. Moore Machine**

32
**Modern Design Register-transfer-level block diagram Datapath**

C: Combinational circuit S: Sequential circuit C S Control Unit Datapath D Q .

33
**FSM Design D or JK or T ?? current state register QX DX Out In clk ？**

next state QX current state DX Out In clk ？ QY ？ DY clk output logic next state logic

34
**Consider the sequence detector**

9/2/2012 – ECE 3561 Lect 7 The same sequence detector to detect a sequence ending in 101 but this time a Moore machine implementation. Moore machine implementation is much the same except that the output designation is now indicated within the state. Copyright Joanne DeGroat, ECE, OSU

35
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

Start in S0 9/2/2012 – ECE 3561 Lect 7 S0 –a state where you have received a non middle 0 or a long string of 0s. Output is 0. Output is indicated within the state not on the transition. Copyright Joanne DeGroat, ECE, OSU

36
**Transitions form state 1**

9/2/2012 – ECE 3561 Lect 7 On a 0 you stay in state 1 On a 1 you transition to state S1. Meaning of S1 – have the 1st 1 of the sequence Copyright Joanne DeGroat, ECE, OSU

37
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

Transition from S1 9/2/2012 – ECE 3561 Lect 7 On a 1 have the first 1 of a sequence – stay in S1. On a 0 now have a sequence that ends in 10 so define a new state S2 and transition to it. Copyright Joanne DeGroat, ECE, OSU

38
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

State S2 9/2/2012 – ECE 3561 Lect 7 S2 has meaning that you have an input sequence that ends in 10 so far. Transitions from S2 0 input – Back to S0 1 input – Valid sequence go to new state S3 which outputs a 1 Copyright Joanne DeGroat, ECE, OSU

39
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

State S3 9/2/2012 – ECE 3561 Lect 7 S3 – have received input sequence that ends in 101. Next input 0 – end of seq (10 so back to S2) 1 – back to S1 (11 so 1st 1) Copyright Joanne DeGroat, ECE, OSU

40
**State Table from State Graph**

9/2/2012 – ECE 3561 Lect 7 Easy to convert state graph to state table Moore machine note output is function of the state Copyright Joanne DeGroat, ECE, OSU

41
**Contrast this to Mealy Machine**

9/2/2012 – ECE 3561 Lect 7 Mealy machine state graph and state table In Mealy machine the output is a function of the state and the current input Copyright Joanne DeGroat, ECE, OSU

42
**Now on to the other example**

9/2/2012 – ECE 3561 Lect 7 Detect the sequences 010 and 1001 and on those output a 1. Starting state on reset is S0 On a 0 transition to S1 - output 0 Have a first 0 On a 1 transition to S3 - output 0 Have a first 1 Copyright Joanne DeGroat, ECE, OSU

43
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

In S1/0 9/2/2012 – ECE 3561 Lect 7 State S1 have the first 0 of a possible 010 On a 1 now have 01 Transition to a new state S2/0 with meaning that you have 01 On a 0 stay in S1/0 Copyright Joanne DeGroat, ECE, OSU

44
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

From S2/0 9/2/2012 – ECE 3561 Lect 7 S2/0 has meaning that you have 01 so far Input is a 0 – Need a new state S4 with meaning that you have received 010 (so output is a 1) and have a 10 for a start of that string. Input is a 1 so the input is 011 – Go to S3 where as this is the first 1. Copyright Joanne DeGroat, ECE, OSU

45
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

From S3/0 9/2/2012 – ECE 3561 Lect 7 S3/0 has meaning that you have the first 1 of the sequence. Input is a 0 – Go to S5 – meaning have 10 Input is a 1 – stay in S3 Copyright Joanne DeGroat, ECE, OSU

46
**Add transitions from S4/1**

9/2/2012 – ECE 3561 Lect 7 S4/1 had meaning that the sequence has been 010 so far. Input is a 0 – Now have 100 – Need a new state with this meaning – S6/0 Input is a 1 – Now have 101 so go back to S2/0 Copyright Joanne DeGroat, ECE, OSU

47
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

Transitions from S5/0 9/2/2012 – ECE 3561 Lect 7 S5/0 means you have 10 so far Input is a 0 – transition to S6/0 – have 100 so far Input is a 1 – now have 101 or the 01 which is the meaning of S2/0 Copyright Joanne DeGroat, ECE, OSU

48
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

State S6/0 9/2/2012 – ECE 3561 Lect 7 S6/0 has meaning that you have a sequence of 100 so far Input is a 1 so have 1001 – a new state S7/1 to signal the sequence 1001. Input is a 0 so have 1000 and back to S1 as you have a first 0. Copyright Joanne DeGroat, ECE, OSU

49
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

From S7/1 9/2/2012 – ECE 3561 Lect 7 S7 has meaning of so you also have the 01 for the start of that sequence Input is a 0 so have 010 – go to S4/1 Input is a 1 so have 011 – go to S3 as you have a first 1. Copyright Joanne DeGroat, ECE, OSU

50
**The state table for each**

9/2/2012 – ECE 3561 Lect 7 For the Mealy Machine Copyright Joanne DeGroat, ECE, OSU

51
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

For the Moore machine 9/2/2012 – ECE 3561 Lect 7 The state table for the Moore machine – output is associated with the state. Present State Next State X=0 Next State X=1 Output Z S0 S1 S3 S2 S4 S5 S6 1 S7 Copyright Joanne DeGroat, ECE, OSU

52
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

The next step 9/2/2012 – ECE 3561 Lect 7 The next step to implementation is state assignment In state assignment the binary code for each state is chosen. Copyright Joanne DeGroat, ECE, OSU

53
**Effect of choosing state assignment**

9/2/2012 – ECE 3561 Lect 7 Choosing one state assignment versus another can have significant implications for circuit implementation. But first – how do you reduce the number of states in the state table? Copyright Joanne DeGroat, ECE, OSU

54
**Example that has sink state**

9/2/2012 – ECE 3561 Lect 7 Programmed Example 14.2 Copyright Joanne DeGroat, ECE, OSU

55
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

Initial states 9/2/2012 – ECE 3561 Lect 7 The start of the state graph Copyright Joanne DeGroat, ECE, OSU

56
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

Step 2 9/2/2012 – ECE 3561 Lect 7 More states Copyright Joanne DeGroat, ECE, OSU

57
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

Complete state graph 9/2/2012 – ECE 3561 Lect 7 Copyright Joanne DeGroat, ECE, OSU

58
**Corresponding State Table**

9/2/2012 – ECE 3561 Lect 7 From the state graph the state table can be generated Copyright Joanne DeGroat, ECE, OSU

59
**Copyright 2012 - Joanne DeGroat, ECE, OSU**

Lecture summary 9/2/2012 – ECE 3561 Lect 7 Have covered state graphs for Mealy and Moore machines Have covered how to transition from state graphs to state tables. Copyright Joanne DeGroat, ECE, OSU

Similar presentations

OK

State Machine Design Shiva choudhary En No.: 140273111002 Electronics and comm. Dept K.I.T.,Jamnagar 1.

State Machine Design Shiva choudhary En No.: 140273111002 Electronics and comm. Dept K.I.T.,Jamnagar 1.

© 2018 SlidePlayer.com Inc.

All rights reserved.

To make this website work, we log user data and share it with processors. To use this website, you must agree to our Privacy Policy, including cookie policy.

Ads by Google