1. Some Characteristics of Spiking Neural P Systems with Anti-Spikes Kamala Krithivasan Department of Computer Science and Engineering Indian Institute of Technology, India kamala@iitm.ac.in Co-authors Padmavati Metta Deepak Garg

2. Outline Spiking Neural P (or SN P) system SN P system with anti-spikes (or SN PA system) SN PA system ◦ As generator / transducer ◦ Example ◦ Simulating Boolean circuits ◦ Simulating Binary Arithmetic operations Conclusion References 2Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 2010

3. Spiking Neural P system is a computational model that has been inspired by neurobiology Distributed and parallel computing model Variant of Membrane System (P System) Uses one type of object called spike ( a ) Computationally complete Spiking Neural P system Ionescu, M., P ă un, Gh., Yokomori, T.: Spiking Neural P Systems, Fund. Infor. 71, 279-308 (2006). 3Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 2010

4. O = { a, ā }, the alphabet. a is called spike and ā is called anti-spike. m neurons - σ 1, σ 2, σ 3,..., σ m Syn - Synapses among the neurons. Spike/anti-spike emitted by a neuron i will pass immediately to all neurons j connected to i through synapses. i 0 – Output neuron Spiking Neural P system with anti-spikes Π =(O, σ 1, σ 2, σ 3,..., σ m, syn, i 0 ) Linqiang, P., P ă un, Gh.: Spiking Neural P Systems with Anti-Spikes, Int. J. of Computers, Communications and Control 4, 273-282, (2009). 4Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 2010

5. Each neuron σ i contains ◦ n i -- initial number of spikes/ anti-spikes ◦ R i -- finite set of rules of the form SN P system with anti-spikes (contd.) 1.Spiking Rules E / b r → b’ – used when a neuron has n spikes/anti-spikes such that b n ∈ L(E) and n ≥ r where b, b’ ∈ { a, ā }, E is a regular expression over { a} or {ā } r ≥ 0, number of b ’s are consumed and a b’ is sent to all neighbouring neurons. They cannot of the form ā r → ā. E is omitted if L(E)=b r., we write b r /b r → b’ as b r → b’ 5Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 2010

6. SN P system with anti-spikes (contd.) 2.Forgetting Rules b s →λ - used when a neuron has s number of b’s s ≥ 0, number of b ’s are forgotten by the neuron. b s should not be in L(E) for any spiking rule E/b r → b’ in R i. 3.Annihilation Rule It is implicitly present in each neuron Whenever a spikes and anti-spike meet in a neuron they annihilate each other using the rule aā →λ and The rule has the highest priority and takes no time. 6Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 2010

7. A global clock is there and all neurons work in parallel but each neuron can use one rule at a time. There can be more than one rule enabled at any time, then a rule is chosen in a non-deterministic way. At any time a neuron can have either spikes or anti-spikes. After receiving spikes/anti-spikes from neighbouring neurons, if a neuron has r spikes and s anti-spikes, it will be left with r-s spikes if r>s or s-r anti-spikes if s>r. The configuration of a system at any time is, where n i is the number of spikes present in neuron σ i if n i >0 or n i anti-spikes if n i <0, 1 ≤ i ≤ m. SN P system with anti-spikes (contd.) 7Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 2010

8. One of the neuron is considered as output neuron From the output neuron, spike/anti-spike is sent to the environment. The moments of time when a spike is emitted by the output neuron are marked with 1, the moments when it emits an anti-spike is marked with 0. The no output moments are ignored. The sequence is called the spike train of the system. The spike train can be the output generated by the system. With a spike train we can also associate various numbers, which can be considered as computed (we also say generated) by an SN P system.  For example distance between the first two spikes of a spike train  Number of spikes present in the output neurons at the end of a halting computation (reaching a configuration where no rule can be used) 8Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 2010 SN PA system as Generator

9. SN PA System as generator– Example Evolution 11, 21 - ā 11, 22 - a 1 2 Output ā r21 : a 2 / a  ā r11 : ā  a r22 : a 2  a a 2 9Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 2010

10. SN PA System as generator– at time t=1 Evolution 11, 21 - ā 11, 22 - a 1 2 Output If the neuron 2 uses the first rule the system will be in the same configuration ā r21 : a 2 / a  ā r11 : ā  a r22 : a 2  a aaā a ā 10Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 2010

11. SN PA System as generator– at any time t Evolution 11, 21 - ā 11, 22 - a 1 2 Output If the neuron 2 uses the second rule the system halts. ā r21 : a 2 / a  ā r11 : ā  a r22 : a 2  a aa a The system generates 0*1, which cannot be generated using simple SN P systems. Ibarra, O. H., Woodworth, S.: Spiking Neural P Systems: Some Characterizations, FCT 2007, LNCS, vol. 4639, pp. 23-37, Springer, Heidelberg (2007). 11Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 2010

12. SN PA system is used as Transducer The system has one or more input and one output neuron. Boolean values 1 and 0 are encoded as spikes and anti-spike respectively. To input 0/1, anti-spike /spike is introduced in the input neurons. The output is 0/1 (hence false/true) if an anti- spike/spike is sent out of the output neuron. 12Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 2010

13. Universal Gates The NAND and NOR gates are universal gates. advantageous since NAND and NOR gates are economical and easier to fabricate and are the basic gates used in all IC digital logic families. Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 201013

14. SN PA system simulating 2-input NAND gate a 4  ā a 3  a a 2  a 1 2 ā  a a  λ ā  a a  a 3 ā  a a  λ ā  a a  a 4 The output is available after three steps ā  a a  ā ā aā a 5 output Input 1 Input 2 in 1in 2 n5out aaa4a4 ā aāa3a3 a āaa3a3 a āāa2a2 a 14Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 2010 1

15. SN PA system simulating 2-input NOR gate Simulation of 2-input NOR gate is similar to NAND gate but replace all rules in neuron 5 with a 4  ā, a 3  ā and a 2  a to output a spike(1) if both the inputs are anti- spikes(0). 15Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 2010 The output of the gate is false (0) only if all the inputs are true(1) and is true if any of the inputs is false. The minimum number of spikes received by the output neuron is n (if all inputs are anti-spikes) and maximum will be 2n (if all inputs are spikes). The rule a 2n  ā in the output neuron fires if all inputs are spikes (1). SN PA system simulating n-input NAND gate

16. a 2n  ā a 2n-1  a a 2n-2  a a n  a 1 2 ā  a a  λ ā  a a  a 2n-1 ā  a a  λ ā  a a  a 2n ā  a a  ā ā aā a 5 output Input 1 Input n 16Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 2010 1

17. Simulation of Boolean formula in SOP form Boolean function can be represented in sum-of-product (SOP) and product-of-sum forms (POS). SOP forms can be implemented using only NAND gates, while POS forms can be implemented using only NOR gates. In either case, implementation requires two levels. The first level is for each term and second level for product or sum of the terms. Consider the Boolean function ¬(x 1  x 2 )  (x 3  x 4 ). It is written in SOP from as ¬x 1  ¬x 2  (x 3  x 4 ) Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 201017

18. SN PA system for SN PA system for ¬x 1  ¬x 2  (x 3  x 4 ) 18Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 2010 x4x4 ¬ x2¬ x2 ¬ x1¬ x1 x3x3 ∏ NAND (1) ∏ (2) ∏ (3) NAND ∏ (4) NAND

19. SN PA system simulating 2’s complement a 3 a 4 /a  a a 2  ā a  ā ā  a 1 2 3 ā aā a a  ā ā aā a outputInput A simple way to find the 2’s complement of a number is to start from the least significant bit keeping every 0 as it is until you reach the first 1 and then complement the rest of the bits after the first 1. 19Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 2010

20. stepinputneuron 2 neuron3output t =0-a3a3 -- t =1ā (0)a3a3 -- t =2ā (0)a4a4 -- t =3a (1)a4a4 a- t =4a (1)a2a2 aā (0) t =5ā (0)āā t =6aaa (1) t =7āā (0) t =8a (1) a 3 a 4 /a  a a 2  ā a  ā ā  a 1 3 ā aā a a  ā ā aā a 2 inputoutput Moves of the SN PA system for the input 01100 SN PA system simulating 2’s complement 20Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 2010

21. SN PA system simulating binary addition a 5 /a 4  a a 4 /a 3  ā a 3  a a 2  ā a  a 1 The output is available after three steps 5 output 21Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 2010 2 ā  a a  λ ā  a a  a 3 ā  a a  λ ā  a a  a 4 ā  a a  ā ā aā a Input 1 Input 2

22. carryin1in2 n5Rule usedoutcarry 00 0 a2a2 a 2  ā 00 00 1 a3a3 a 3  a 10 01 0 a3a3 10 01 1 a4a4 a 4 /a 3  ā 01 10 0 a3a3 a 3  a 10 10 1 a4a4 a 4 /a 3  ā 01 11 0 a4a4 01 11 1 a5a5 a 5 /a 4  a 11 1--a a  a 10 SN PA system simulating binary addition A spike is left in the output neuron to represent the carry 22Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 2010

23. Conclusion Spiking neural P systems are used to simulate fundamental gates in, Ionescu, M., Sburlan, D.: Some Applications of Spiking Neural P systems, J. of Computing and Informatics 27 515-528 (2008). with two spikes emitting out of the system encoded as 1 and one spike as 0. SN P system with anti-spikes provides a natural way to represent the binary digits using spike and anti-spike. Simulating a Boolean circuit with universal gates does not require synchronizing module. Some languages that cannot be generated using simple SN P systems can be generated using SN PA systems. Here we also consider SN P system with anti-spikes as simple arithmetic device that can perform the arithmetic operations like 2’s complement, addition and subtraction with input and output in binary form. 23Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 2010

24. References Gutiérréz-Naranjo, M. A., Leporati, A.: First Steps Towards a CPU Made of Spiking Neural P Systems, Int. J. of Computers, Communications and Control 4 244-252 (2009). Ibarra, O. H., Woodworth, S.: Spiking Neural P Systems: Some Characterizations, FCT 2007, LNCS, vol. 4639, pp. 23-37, Springer, Heidelberg (2007). Ionescu, M., Păun, Gh., Yokomori, T.: Spiking Neural P Systems, Fund. Infor. 71, 279- 308 (2006). Ionescu, M., Sburlan, D.: Some Applications of Spiking Neural P systems, J. of Computing and Informatics 27 515-528 (2008). Linqiang, P., Păun, Gh.: Spiking Neural P Systems with Anti-Spikes, Int. J. of Computers, Communications and Control 4, 273-282, (2009). Păun, Gh.: Spiking Neural P Systems Used as Acceptors and Transducers, CIAA, LNCS, vol. 4783, pp. 1-4, Springer, Heidelberg (2007). 24Padmavati Metta, Kamala Krithivasan and Deepak Garg CMC 2010

25. Thank you !