1. WMC8 – Thessaloniki, Greece Some Applications of Spiking Neural P Systems Mihai Ionescu 1 & Dragoş Sburlan 2 1 URV, Research Group on Mathematical Linguistics, Spain 2 Ovidius University, Faculty of Mathematics and Informatics, Romania

2. WMC8 – Thessaloniki, Greece Outline 1. On Spiking Neural P Systems Definition. Example. Exhaustive use of the rules. Example. 2. Simulating Logical Gates and Circuits NOT gate Example of a circuit 3. A Sorting Algorithm Example

3. WMC8 – Thessaloniki, Greece Definition 1 : Π = (O, σ 1, …, σ m, syn, i 0 ) where: 1. O = { a } (the alphabet of objects contains only one object); 1. On Spiking Neural P Systems 2. σ 1, …, σ m are neurons, identified by tuples σ i = (n i,R i ), 1 ≤ i ≤ m, where: a) n i ≥ 0 a2a2 a 1 M. Ionescu, Gh. Paun, T. Yokomori, Spiking Neural P Systems, Fundamenta Informaticae, 71, 2-3(2006), 279-308.

4. WMC8 – Thessaloniki, Greece a2a2 a b) R i is a finite set of rules: (1) E/a r → a; t, where E is a regular expresion over O, r ≥ 1, t ≥ 0; (2) a s → λ, for some s ≥ 1, a s ∉ L(E) for any rule of type (1) from R i a 2 ->a;0 (aa)*/a 3 ->a;1 a->a;0 a 2 ->λ 1. On Spiking Neural P Systems Definition (continued): Π = (O, σ 1, …, σ m, syn, i 0 )...

5. WMC8 – Thessaloniki, Greece a2a2 a 1. On Spiking Neural P Systems a 2 ->a; 0 (aa)*/a 3 ->a;1 a->a;0 a 2 ->λ Definition (continued): Π = (O, σ 1, …, σ m, syn, i 0 )... c) syn ⊆ {1, 2, … m} x {1, 2, … m}, with (i,i) ∉ syn, for 1≤ i ≤ m; d) i 0 € {1, 2, … m} indicates the output neuron Spik 2 P m (rule d, cons p, forg q )

6. WMC8 – Thessaloniki, Greece Example – Initial Configuration a 2 a 2 → a;0 a → λ a 2 a 2 → a;0 a 2 → a;1 a 2 a 2 → a;0 a → λ a 2 a 2 → a;0 a 3 → λ 1 2 3 4 1. On Spiking Neural P Systems

7. WMC8 – Thessaloniki, Greece Example – Step 1 – used rules SPIKE a 2 a 2 → a;0 a → λ a 2 a 2 → a;0 a 2 → a;1 a 2 a 2 → a;0 a → λ a 2 a 2 → a;0 a 3 → λ 1 2 3 4 1. On Spiking Neural P Systems

8. WMC8 – Thessaloniki, Greece Example – Step 1 – result a 2 a 3 a 2 → a;0 a → λ a 1 a 2 a 2 → a;0 a 2 → a;1 a 1 a 3 a 2 → a;0 a → λ a 1 a 2 a 3 a 2 → a;0 a 3 → λ 1 2 3 4 1. On Spiking Neural P Systems

9. WMC8 – Thessaloniki, Greece Example – Step 2 – used rules a 2 a 2 → a;0 a → λ a 2 a 2 → a;0 a 2 → a;1 a 2 a 2 → a;0 a → λ a 3 a 2 → a;0 a 3 → λ 1 2 3 4 1. On Spiking Neural P Systems

10. WMC8 – Thessaloniki, Greece Example – Step 2 – result a 2 a 2 → a;0 a → λ a 2 → a;0 a 2 → a;1 a 1 a 2 → a;0 a → λ a 1 a 2 a 2 → a;0 a 3 → λ 1 2 3 4 1. On Spiking Neural P Systems

11. WMC8 – Thessaloniki, Greece Example – Step 3 – used rules SPIKE a a 2 → a;0 a → λ a 2 → a;0 a 2 → a;1 a a 2 → a;0 a → λ a 2 a 2 → a;0 a 3 → λ 1 2 3 4 1. On Spiking Neural P Systems

12. WMC8 – Thessaloniki, Greece Example – Step 3 – result a 3 a 2 → a;0 a → λ a 2 → a;0 a 2 → a;1 a 3 a 2 → a;0 a → λ a 3 a 2 → a;0 a 3 → λ 1 2 3 4 3-1 = 2 1. On Spiking Neural P Systems

13. WMC8 – Thessaloniki, Greece Results: NFIN = Spik 2 P 1 (rule *, cons 1, forg 0 ) = Spik 2 P 1 (rule *, cons *, forg * ) = Spik 2 P 2 (rule *, cons *, forg * ) Spik 2 P * (rule k, cons p, forg q ) = NRE, for all k ≥ 2, p ≥ 3, q ≥ 3. SLIN 1 = Spik 2 P * (rule k, cons p, forg q, bound s ), for all k ≥ 3, p ≥ 3, q ≥ 3, and s ≥ 3 1. Spiking Neural P Systems

14. WMC8 – Thessaloniki, Greece Exhaustive use of the rules. Example a 5 a(aa)*/a → a;0 a(aa)*/a 2 → a;0 1. On Spiking Neural P Systems

15. WMC8 – Thessaloniki, Greece Exhaustive use of the rules. Example a 5 a(aa)*/a → a;0 a(aa)*/a 2 → a;0 1. On Spiking Neural P Systems

16. WMC8 – Thessaloniki, Greece Exhaustive use of the rules. Example a(aa)*/a → a;0 a(aa)*/a 2 → a;0 1. On Spiking Neural P Systems a5a5

17. WMC8 – Thessaloniki, Greece Exhaustive use of the rules. Example a 5 a(aa)*/a → a;0 a(aa)*/a 2 → a;0 1. On Spiking Neural P Systems

18. WMC8 – Thessaloniki, Greece Exhaustive use of the rules. Example a a(aa)*/a → a;0 a(aa)*/a 2 → a;0 1. On Spiking Neural P Systems a2a2

19. WMC8 – Thessaloniki, Greece 2. Simulating Logical Gates and Circuits Codification: – Boolean value 1 : aa – Boolean value 0 : a

20. WMC8 – Thessaloniki, Greece 2. Simulating Logical Gates and Circuits NOT Gate: a a 2 /a → a;0 a 3 → a;0 1 a/a → a;0 a 2 /a 2 → a;0 2

21. WMC8 – Thessaloniki, Greece 2. Simulating Logical Gates and Circuits NOT Gate: 1→0 aaa a 2 /a → a;0 a 3 → a;0 1 a/a → a;0 a 2 /a 2 → a;0 2

22. WMC8 – Thessaloniki, Greece 2. Simulating Logical Gates and Circuits NOT Gate: 1→0 a 2 /a → a;0 a 3 → a;0 1 a a/a → a;0 a 2 /a 2 → a;0 2 a

23. WMC8 – Thessaloniki, Greece 2. Simulating Logical Gates and Circuits NOT Gate: 0→1 a a 2 /a → a;0 a 3 → a;0 1 a/a → a;0 a 2 /a 2 → a;0 2

24. WMC8 – Thessaloniki, Greece 2. Simulating Logical Gates and Circuits NOT Gate: 0→1 a 2 /a → a;0 a 3 → a;0 1 aa a/a → a;0 a 2 /a 2 → a;0 2 aa

25. WMC8 – Thessaloniki, Greece 2. Simulating Logical Gates and Circuits Lemma 1: – Boolean AND gate can be simulated by SN P systems using one neuron and no delay on the rules, in one step. Lemma 2: – Boolean OR gate can be simulated by SN P systems using one neuron and no delay on the rules, in one step. Lemma 3: – Boolean NOT gate can be simulated by SNP systems using two neurons, no delay on the rules, in two steps.

26. WMC8 – Thessaloniki, Greece 2. Simulating Logical Gates and Circuits Circuits.Example: f:{0,1} 4 → {0,1} f(x 1,x 2,x 3,x 4 )=(x 1 Λ x 2 ) V ¬(x 3 Λ x 4 )

27. WMC8 – Thessaloniki, Greece 2. Simulating Logical Gates and Circuits Circuits.Example: f:{0,1} 4 → {0,1} f(x 1,x 2,x 3,x 4 )=(x 1 Λ x 2 ) V ¬(x 3 Λ x 4 ) AND

28. WMC8 – Thessaloniki, Greece 2. Simulating Logical Gates and Circuits Circuits.Example: f:{0,1} 4 → {0,1} f(x 1,x 2,x 3,x 4 )=(x 1 Λ x 2 ) V ¬(x 3 Λ x 4 ) AND NOT

29. WMC8 – Thessaloniki, Greece 2. Simulating Logical Gates and Circuits Circuits.Example: f:{0,1} 4 → {0,1} f(x 1,x 2,x 3,x 4 )=(x 1 Λ x 2 ) V ¬(x 3 Λ x 4 ) AND NOT SYNC

30. WMC8 – Thessaloniki, Greece 2. Simulating Logical Gates and Circuits Circuits.Example: f:{0,1} 4 → {0,1} f(x 1,x 2,x 3,x 4 )=(x 1 Λ x 2 ) V ¬(x 3 Λ x 4 ) AND NOT SYNC OR

31. WMC8 – Thessaloniki, Greece 2. Simulating Logical Gates and Circuits Circuits.Example: AND NOT SYNC OR

32. WMC8 – Thessaloniki, Greece 2. Simulating Logical Gates and Circuits Theorem: Every Boolean circuit α, whose underlying graph structure is a rooted tree, can be simulated by a SN P system, Π α, in linear time. Π α is constructed from SN P systems of type Π AND, Π OR and Π NOT, by reproducing in the architecture of the neural structure, the structure of the tree associated to the circuit.

33. WMC8 – Thessaloniki, Greece 2. Simulating Logical Gates and Circuits – Further Ideas Arbitrary circuits, hence not necessary rooted tree.

34. WMC8 – Thessaloniki, Greece 3. A (Simple) Sorting Algorithm Example. 1,3,2 Initial configuration a*/a→a;0 a 3 →a;0 a 2 →λ a→λ a*/a→a;0 a 2 →a;0 a 3 →λ a→λ a→a;0 a 2 →λ a 3 →λ a a3a3 a2a2

35. WMC8 – Thessaloniki, Greece 3. A (Simple) Sorting Algorithm Example. 1,3,2Step 1 a*/a→a;0 a 3 →a;0 a 2 →λ a→λ a*/a→a;0 a 2 →a;0 a 3 →λ a→λ a→a;0 a 2 →λ a 3 →λ a2a2 a a3a3 a3a3 a3a3

36. WMC8 – Thessaloniki, Greece 3. A (Simple) Sorting Algorithm Example. 1,3,2Step 2 a*/a→a;0 a 3 →a;0 a 2 →λ a→λ a*/a→a;0 a 2 →a;0 a 3 →λ a→λ a→a;0 a 2 →λ a 3 →λ a a2a2 a2a2 a2a2 aaa

37. WMC8 – Thessaloniki, Greece 3. A (Simple) Sorting Algorithm Example. 1,3,2Step 3 a*/a→a;0 a 3 →a;0 a 2 →λ a→λ a*/a→a;0 a 2 →a;0 a 3 →λ a→λ a→a;0 a 2 →λ a 3 →λ a a a aa2a2 a2a2

38. WMC8 – Thessaloniki, Greece 3. A (Simple) Sorting Algorithm Example. 1,3,2Step 4 a*/a→a;0 a 3 →a;0 a 2 →λ a→λ a*/a→a;0 a 2 →a;0 a 3 →λ a→λ a→a;0 a 2 →λ a 3 →λ aa2a2 a3a3

39. WMC8 – Thessaloniki, Greece 3. A (Simple) Sorting Algorithm Example. 1,3,2Step 4 a*/a→a;0 a 3 →a;0 a 2 →λ a→λ a*/a→a;0 a 2 →a;0 a 3 →λ a→λ a→a;0 a 2 →λ a 3 →λ aa2a2 a3a3

40. WMC8 – Thessaloniki, Greece 2. A Sorting Algorithm Theorem : SN P systems can sort a vector of natural numbers where each number is given as number of spikes introduced in the neural structure. Remarks: - time complexity: O(T), T is the magnitude of the numbers to be sorted - Further research: magnitude, improvements of time complexity, number of neurons

41. WMC8 – Thessaloniki, Greece Thank You !